This paper presents a novel readout system for wireless passive pressure sensors based on the inductively coupled inductor and cavity （LC） resonant circuits. The proposed system consists of a reader antenna inductiv...This paper presents a novel readout system for wireless passive pressure sensors based on the inductively coupled inductor and cavity （LC） resonant circuits. The proposed system consists of a reader antenna inductively coupled to the sensor circuit, a readout circuit, and a personal computer （PC） post processing unit. The readout circuit generates a voltage signal representing the sensor＇s capacitance. The frequency of the reader antenna driving signal is a constant, which is equal to the sensor＇s resonant frequency at zero pressure. Based on mechanical and electrical modeling, the pressure sensor design based on the high temperature co-fired ceramic （HTCC） technology is conducted and discussed. The functionality and accuracy of the readout system are tested with a voltage-capacitance measurement system and demonstrated in a realistic pressure measurement environment, so that the overall performance and the feasibility of the readout system are proved.展开更多
We present a new sense amplifier circuit for EEPROM memory. The topology of the sense amplifier uses a voltage sensing method,having low cost and low power consumption as well as high reliability. The sense amplifier ...We present a new sense amplifier circuit for EEPROM memory. The topology of the sense amplifier uses a voltage sensing method,having low cost and low power consumption as well as high reliability. The sense amplifier was implemented in an EEPROM realized with an SMIC 0.35-μm 2P3M CMOS embedded EEPROM process. Under the condition that the power supply is 3.3 V,simulation results showed that the charge time is 35 ns in the proposed sense amplifier,and that the maximum average current consumption during the read period is 40 μA. The novel topology allows the circuit to function with power supplies as low as 1.4 V. The sense amplifier has been implemented in 2-kb EEPROM memory for RFID tag IC applications,and has a silicon area of only 240 μm2.展开更多
A multi-stage dual replica bit-line delay （MDRBD） technique is proposed for reducing access time by suppressing the sense-amplifier enable （SAE） timing variation of low voltage static randomaccess memory （SRAM） ...A multi-stage dual replica bit-line delay （MDRBD） technique is proposed for reducing access time by suppressing the sense-amplifier enable （SAE） timing variation of low voltage static randomaccess memory （SRAM） applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-fine （RBL） capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology （Taiwan Semiconductor Manufacturing Company, Taiwan）.展开更多
文摘This paper presents a novel readout system for wireless passive pressure sensors based on the inductively coupled inductor and cavity （LC） resonant circuits. The proposed system consists of a reader antenna inductively coupled to the sensor circuit, a readout circuit, and a personal computer （PC） post processing unit. The readout circuit generates a voltage signal representing the sensor＇s capacitance. The frequency of the reader antenna driving signal is a constant, which is equal to the sensor＇s resonant frequency at zero pressure. Based on mechanical and electrical modeling, the pressure sensor design based on the high temperature co-fired ceramic （HTCC） technology is conducted and discussed. The functionality and accuracy of the readout system are tested with a voltage-capacitance measurement system and demonstrated in a realistic pressure measurement environment, so that the overall performance and the feasibility of the readout system are proved.
基金Project (No. 2006AA01Z226) supported by the Hi-Tech Research and Development Program (863) of China
文摘We present a new sense amplifier circuit for EEPROM memory. The topology of the sense amplifier uses a voltage sensing method,having low cost and low power consumption as well as high reliability. The sense amplifier was implemented in an EEPROM realized with an SMIC 0.35-μm 2P3M CMOS embedded EEPROM process. Under the condition that the power supply is 3.3 V,simulation results showed that the charge time is 35 ns in the proposed sense amplifier,and that the maximum average current consumption during the read period is 40 μA. The novel topology allows the circuit to function with power supplies as low as 1.4 V. The sense amplifier has been implemented in 2-kb EEPROM memory for RFID tag IC applications,and has a silicon area of only 240 μm2.
基金Project supported by the National Natural Science Foundation of China （No. 61474001）
文摘A multi-stage dual replica bit-line delay （MDRBD） technique is proposed for reducing access time by suppressing the sense-amplifier enable （SAE） timing variation of low voltage static randomaccess memory （SRAM） applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-fine （RBL） capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology （Taiwan Semiconductor Manufacturing Company, Taiwan）.
