电压频控中抗强干扰软件关联缺陷检测

针对传统电压频控软件缺陷检测技术未考虑软件缺陷分类,存在检测精度低的问题,提出一种电压频控中抗强干扰软件关联缺陷检测技术;对软件关联缺陷检测原理进行分析,采用判别函数对待测软件样本进行识别,引入统计模式识别算法处理软件原始数据,依据关联缺陷概率分配,确定关联缺陷类别,计算缺陷特征值,利用贝叶斯分类器对关联缺陷进行划分,完成抗强干扰软件关联缺陷的分类,从而实现关联缺陷的高精度检测;实验结果表明,该检测技术对软件缺陷进行准确分类,在保证强抗干扰性的前提下,有效提高了检测精度。

Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector

A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.

A Low Jitter PLL in a 90nm CMOS Digital Process

A low jitter phase-locked loop （PLL） that does not need analog resistors and capacitors is designed and fabrica- ted in a 90nm CMOS digital process. The metal parasitic capacitor is used in the PLL loop filter. Test results show that when the PLL is locked on 1. 989GHz, the RMS jitter is 3. 7977ps, the peak-to-peak jitter is 31. 225ps, and the power con- sumption is about 9mW. The locked output frequency range is from 125MHz to 2.7GHz.

Low phase noise LC VCO design in CMOS technology

This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.

Research on CMOS Mm-Wave Circuits and Systems for Wireless Communications

This paper lenges in the design of discusses some chal- millimeter-wave （mln- wave） circuits and systems for 5th generation （5G） wireless systems in CMOS process. The properties of some passive and active devices such as inductors, capacitors, transmission lines, translbrmers and transistors in mm-wave frequency band are discussed. Self-healing technique dealing with PVT variation, res- onant mode switching technique to enhance frequency tuning range of voltage controlled oscillator （VCO） and dual mode technique for power amplifier （PA） efficiency enhancement are introduced. At last, A fully-integrated 60 GHz 5 Gb/s QPSK transceiver with the transmit/receive （T/R） switch in 65nm CMOS process is introduced. The measured error vector magnitude （EVM） of the TX is -21.9 dB while the bit error rate （BER） of the RX with a -52 dBm sine-wave input is below 8e-7 when transmitting/receiving 5 Gb/s data. The transceiver is powered by 1.0 V and 1.2 V supply （except the phase-frequency detector and charge-pump in the frequency synthesizer which are powered by 2.5 V supply） and con- sumes 135 mW in TX mode and 176 mW in RX mode.

1.0 V low voltage CMOS mixer based on voltage control load technique

A CMOS active mixer based on voltage control load technique which can operate at 1.0 V supply voltage was proposed, and its operation principle, noise and linearity analysis were also presented. Contrary to the conventional Gilbert-type mixer which is based on RF current-commutating, the load impedance in this proposed mixer is controlled by the LO signal, and it has only two stacked transistors at each branch which is suitable for low voltage applications. The mixer was designed and fabricated in 0.18 tam CMOS process for 2.4 GHz ISM band applications. With an input of 2.44 GHz RF signal and 2.442 GHz LO signal, the measurement specifications of the proposed mixer are： the conversion gain （Gc） is 5.3 dB, the input-referred third-order intercept point （PIIP3） is 4.6 dBm, the input-referred 1 dB compression point （P1dB） is --7.4 dBm, and the single-sideband noise figure （NFSSB） is 21.7 dB.

Acquisition algorithm assisted by AGC control voltage for DSSS signals

An appropriate acquisition configuration in terms of signal quality can optimize the acquisition performance. In view of this, a new approach of acquisition assisted by the control voltage of automatic gain control(AGC) is proposed. This approach judges the signal power according to the AGC control voltage and switches the working modes correspondingly and adaptively. Non-coherent accumulation times and the detection threshold are reconfigured according to the working mode. Theoretical derivation and verification by simulation in typical situations are provided, and the algorithm is shown to be superior in terms of the mean acquisition time, especially in strong signal scenarios compared with the conventional algorithm.