A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and ...A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.展开更多
This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further t...This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further through adopting the full custom design method.The proposed word aligner has fabricated in 0.18μm CMOS technology with total area of 1.075 ×0.775mm^2￣ including I/O pad.Measurement results show that this circuit achieves the maximum data rate of 14.5Gb/s,while consuming a total power of 34.9mW from a 1.8V supply.展开更多
文摘A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA10305)
文摘This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further through adopting the full custom design method.The proposed word aligner has fabricated in 0.18μm CMOS technology with total area of 1.075 ×0.775mm^2￣ including I/O pad.Measurement results show that this circuit achieves the maximum data rate of 14.5Gb/s,while consuming a total power of 34.9mW from a 1.8V supply.
