A four-stage monolithic microwave integrated circuits （MMIC） low noise amplifier （LNA） operating from 23 to 36GHz is reported using commercially available 0.15μm PHEMT technology. The LNA is self-biased. To achie...A four-stage monolithic microwave integrated circuits （MMIC） low noise amplifier （LNA） operating from 23 to 36GHz is reported using commercially available 0.15μm PHEMT technology. The LNA is self-biased. To achieve a low noise characteristic, careful optimizations of gate width are performed to reduce gate resistance. Absorption circuits and an elaborate bias structure with a resistor-capacitor network are employed to improve stability. Multiple resonance points and negative feedback technologies are used to widen the bandwidth. Measurements show a noise figure （NF） of less than 2.0dB,and the lowest NF is only 1.6dB at a frequency of 31GHz. In the whole operation band,the LNA has a gain of higher than 26dB,and an input return loss and output return loss of more than 11 and 13dB,respectively. The output power at ldB compression gain of 36GHz is about 14dBm. The chip area is 2.4mm ×1mm.展开更多
In planning and executing marine controlled-source electromagnetic methods, seafloor electromagnetic receivers must overcome the problems of noise, clock drift, and power consumption. To design a receiver that perform...In planning and executing marine controlled-source electromagnetic methods, seafloor electromagnetic receivers must overcome the problems of noise, clock drift, and power consumption. To design a receiver that performs well and overcomes the abovementioned problems, we performed forward modeling of the E-field abnormal response and established the receiver＇s characteristics. We describe the design optimization and the properties of each component, that is, low-noise induction coil sensor, low-noise Ag/AgCI electrode, low-noise chopper amplifier, digital temperature-compensated crystal oscillator module, acoustic telemetry modem, and burn wire system. Finally, we discuss the results of onshore and offshore field tests to show the effectiveness of the developed seafloor electromagnetic receiver and its performance： typical E-field noise of 0.12 nV/m/rt（Hz） at 0.5 Hz, dynamic range higher than 120 dB, clock drift lower than 1 ms/day, and continuous operation of at least 21 days.展开更多
A single power supply common-gate （CG） current mode transimpedance preamplifier （TIA） is developed with a 0.5μm GaAs PHEMT process. The amplifier has a measured - 3dB bandwidth of 7. 5GHz and a transimpedance gai...A single power supply common-gate （CG） current mode transimpedance preamplifier （TIA） is developed with a 0.5μm GaAs PHEMT process. The amplifier has a measured - 3dB bandwidth of 7. 5GHz and a transimpedance gain of 45dBΩ. Both the input and output voltage standing wave ratios （VSWR） are less than 2 within the bandwidth. The equivalent input noise current spectral density varies from 14.3 to 22pA/√Hz, with an average value of 17. 2pA/√Hz. Having a timing jitter of 14ps and eye amplitude of about 138mV,the measured output eye diagram for 10Gb/s NRZ pseudorandom binary sequence （PRBS） is clear and satisfactory.展开更多
A CMOS radio frequency low noise amplifier with high linearity and low operation voltage of less than 1.0V is presented.In this circuit,an auxiliary MOSFET in the triode region is used to boost the linearity.Simulatio...A CMOS radio frequency low noise amplifier with high linearity and low operation voltage of less than 1.0V is presented.In this circuit,an auxiliary MOSFET in the triode region is used to boost the linearity.Simulation shows that this method can boost the input-referred 3rd-order intercept point with much less power dissipation than that of traditional power/linearity tradeoff solution which pays at least 1dB power for 1dB linearity improvement.It is also shown that the size of the common-gate PMOS transistor needs to be optimized to reduce its loaded input impedance so as not to degrade the linearity due to high voltage gain at its source terminal.The simulation is carried out with TSMC 0.18μm RF CMOS technology and SpectreRF.展开更多
A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this for...A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5 2GHz CMOS LNA.展开更多
This paper deals with internally generated noise of bioelectric amplifiers that are usually used for processing of bioelectric events. The main purpose of this paper is to present a procedure for analysis of the effec...This paper deals with internally generated noise of bioelectric amplifiers that are usually used for processing of bioelectric events. The main purpose of this paper is to present a procedure for analysis of the effects of internal noise generated by the active circuits and to evaluate the output noise of the author's new designed bioelectric amplifier that caused by internal effects to the amplifier circuit itself in order to compare it with the noise generated by conventional amplifiers. The obtained analysis results of internally generated noise showed that the total output noise of bioelectric active circuits does not increase when some of their resistors have a larger value. This behavior is caused by the different transfer functions for the signal and the respective noise sources associated with these resistors. Moreover, the new designed bioelectric amplifier has an output noise less than that for conventional amplifiers. The obtained analysis results were also experimentally verified and the final conclusions were drawn.展开更多
This paper describes a CMOS low noise amplifier （LNA） plus the quadrature mixers intended for use in the front-end of portable global positioning system （GPS） receivers. The LNA makes use of an inductively degener...This paper describes a CMOS low noise amplifier （LNA） plus the quadrature mixers intended for use in the front-end of portable global positioning system （GPS） receivers. The LNA makes use of an inductively degenerated input stage and power-constrained simultaneous noise and input matching techniques. The quadrature mixers are based on a Gil- bert cell type. The circuits are implemented in a TSMC 0.18μm RF CMOS process. Measurement results show that a voltage conversion gain of 35dB is achieved with a cascade noise and an input return loss of - 22.3dB. The fully differential figure of 2.4dB,an input ldB compression point of - 22dBm, circuits only draw 5.4mW from a 1.8V supply.展开更多
文摘A four-stage monolithic microwave integrated circuits （MMIC） low noise amplifier （LNA） operating from 23 to 36GHz is reported using commercially available 0.15μm PHEMT technology. The LNA is self-biased. To achieve a low noise characteristic, careful optimizations of gate width are performed to reduce gate resistance. Absorption circuits and an elaborate bias structure with a resistor-capacitor network are employed to improve stability. Multiple resonance points and negative feedback technologies are used to widen the bandwidth. Measurements show a noise figure （NF） of less than 2.0dB,and the lowest NF is only 1.6dB at a frequency of 31GHz. In the whole operation band,the LNA has a gain of higher than 26dB,and an input return loss and output return loss of more than 11 and 13dB,respectively. The output power at ldB compression gain of 36GHz is about 14dBm. The chip area is 2.4mm ×1mm.
基金sponsored by the 863 Program(No.2009AA09A2012012AA09A201)+1 种基金China Geological Survey Project(No.201100307)the Fundamental Research Funds of the Ministry of Education for the Central Universities(No.2652011249)
文摘In planning and executing marine controlled-source electromagnetic methods, seafloor electromagnetic receivers must overcome the problems of noise, clock drift, and power consumption. To design a receiver that performs well and overcomes the abovementioned problems, we performed forward modeling of the E-field abnormal response and established the receiver＇s characteristics. We describe the design optimization and the properties of each component, that is, low-noise induction coil sensor, low-noise Ag/AgCI electrode, low-noise chopper amplifier, digital temperature-compensated crystal oscillator module, acoustic telemetry modem, and burn wire system. Finally, we discuss the results of onshore and offshore field tests to show the effectiveness of the developed seafloor electromagnetic receiver and its performance： typical E-field noise of 0.12 nV/m/rt（Hz） at 0.5 Hz, dynamic range higher than 120 dB, clock drift lower than 1 ms/day, and continuous operation of at least 21 days.
文摘A single power supply common-gate （CG） current mode transimpedance preamplifier （TIA） is developed with a 0.5μm GaAs PHEMT process. The amplifier has a measured - 3dB bandwidth of 7. 5GHz and a transimpedance gain of 45dBΩ. Both the input and output voltage standing wave ratios （VSWR） are less than 2 within the bandwidth. The equivalent input noise current spectral density varies from 14.3 to 22pA/√Hz, with an average value of 17. 2pA/√Hz. Having a timing jitter of 14ps and eye amplitude of about 138mV,the measured output eye diagram for 10Gb/s NRZ pseudorandom binary sequence （PRBS） is clear and satisfactory.
文摘A CMOS radio frequency low noise amplifier with high linearity and low operation voltage of less than 1.0V is presented.In this circuit,an auxiliary MOSFET in the triode region is used to boost the linearity.Simulation shows that this method can boost the input-referred 3rd-order intercept point with much less power dissipation than that of traditional power/linearity tradeoff solution which pays at least 1dB power for 1dB linearity improvement.It is also shown that the size of the common-gate PMOS transistor needs to be optimized to reduce its loaded input impedance so as not to degrade the linearity due to high voltage gain at its source terminal.The simulation is carried out with TSMC 0.18μm RF CMOS technology and SpectreRF.
文摘A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5 2GHz CMOS LNA.
文摘This paper deals with internally generated noise of bioelectric amplifiers that are usually used for processing of bioelectric events. The main purpose of this paper is to present a procedure for analysis of the effects of internal noise generated by the active circuits and to evaluate the output noise of the author's new designed bioelectric amplifier that caused by internal effects to the amplifier circuit itself in order to compare it with the noise generated by conventional amplifiers. The obtained analysis results of internally generated noise showed that the total output noise of bioelectric active circuits does not increase when some of their resistors have a larger value. This behavior is caused by the different transfer functions for the signal and the respective noise sources associated with these resistors. Moreover, the new designed bioelectric amplifier has an output noise less than that for conventional amplifiers. The obtained analysis results were also experimentally verified and the final conclusions were drawn.
文摘This paper describes a CMOS low noise amplifier （LNA） plus the quadrature mixers intended for use in the front-end of portable global positioning system （GPS） receivers. The LNA makes use of an inductively degenerated input stage and power-constrained simultaneous noise and input matching techniques. The quadrature mixers are based on a Gil- bert cell type. The circuits are implemented in a TSMC 0.18μm RF CMOS process. Measurement results show that a voltage conversion gain of 35dB is achieved with a cascade noise and an input return loss of - 22.3dB. The fully differential figure of 2.4dB,an input ldB compression point of - 22dBm, circuits only draw 5.4mW from a 1.8V supply.
