基于0.18 mm工艺设计了一种可集成到低电源电压数字IC或数模混合IC的上电复位电路。该POR(Power On Reset)具有电源上电和掉电检测功能,且对电源上电的速度不敏感,故可通过使用迟滞比较器实现对电源噪声的免疫。corner仿真结果表明,该...基于0.18 mm工艺设计了一种可集成到低电源电压数字IC或数模混合IC的上电复位电路。该POR(Power On Reset)具有电源上电和掉电检测功能,且对电源上电的速度不敏感,故可通过使用迟滞比较器实现对电源噪声的免疫。corner仿真结果表明,该电路可以实现大于100 ms的延时。相比于传统POR,该电路工作电压低、性能可靠、结构简单。展开更多
This paper presents an innovative switched-mode auto gain control （AGC） circuit with internally created reset module for DC-10Mb/s burst-mode unbalanced （BMU） optical data transmission. Conventional AGC circuit is...This paper presents an innovative switched-mode auto gain control （AGC） circuit with internally created reset module for DC-10Mb/s burst-mode unbalanced （BMU） optical data transmission. Conventional AGC circuit is inappropriate for BMU data transmission because it is based on average level detection and requires considerable time to settle on a predefined gain. Therefore, we adopt a fast switched-mode AGC based on peak level detection. After the gain is adjusted, the peak level detectors need to re-detect the peak level of the input signal. Thus, we develop an internally created reset module. This AGC with reset module exhibits a fast operation and achieves an adjusted stable gain within one-bit, avoiding any bit loss up to 10Mb/s data rate. During power-up, the peak level detectors possibly hold an uncertain level resulting in the bit-errors. We propose a power-up reset circuit to solve this problem. Designed in a 0.5μm CMOS technology, the circuit achieves an optical sensitivity of better than -30dBm and a wide dynamic range of over 30dB with a power dissipation of only 30 mW from a 5V supply.展开更多
文摘基于0.18 mm工艺设计了一种可集成到低电源电压数字IC或数模混合IC的上电复位电路。该POR(Power On Reset)具有电源上电和掉电检测功能,且对电源上电的速度不敏感,故可通过使用迟滞比较器实现对电源噪声的免疫。corner仿真结果表明,该电路可以实现大于100 ms的延时。相比于传统POR,该电路工作电压低、性能可靠、结构简单。
基金Supported by the Natural Science Foundation of Jiangsu Province （ BK2010411 ） and the National International Cooperation Project of China-Korea （2011DFA11310）.
文摘This paper presents an innovative switched-mode auto gain control （AGC） circuit with internally created reset module for DC-10Mb/s burst-mode unbalanced （BMU） optical data transmission. Conventional AGC circuit is inappropriate for BMU data transmission because it is based on average level detection and requires considerable time to settle on a predefined gain. Therefore, we adopt a fast switched-mode AGC based on peak level detection. After the gain is adjusted, the peak level detectors need to re-detect the peak level of the input signal. Thus, we develop an internally created reset module. This AGC with reset module exhibits a fast operation and achieves an adjusted stable gain within one-bit, avoiding any bit loss up to 10Mb/s data rate. During power-up, the peak level detectors possibly hold an uncertain level resulting in the bit-errors. We propose a power-up reset circuit to solve this problem. Designed in a 0.5μm CMOS technology, the circuit achieves an optical sensitivity of better than -30dBm and a wide dynamic range of over 30dB with a power dissipation of only 30 mW from a 5V supply.
