An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasit...An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.展开更多
A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase...A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.展开更多
基金Supported by National Science and Technology Major Project of China(No.2012ZX03004008)
文摘An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.
基金Supported by National Natural Science Foundation of China (No.60806010,No.60976030)
文摘A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.
