基于最小有功注入策略,提出一种新型的动态电压恢复器(dynamic voltage restorer,DVR)结构,其主要结构由基本的级联H桥逆变器和并联的晶闸管开关电感组成。文章分析了新型DVR的电路拓扑和基本原理,推导了最小有功注入策略,分析了DVR的...基于最小有功注入策略,提出一种新型的动态电压恢复器(dynamic voltage restorer,DVR)结构,其主要结构由基本的级联H桥逆变器和并联的晶闸管开关电感组成。文章分析了新型DVR的电路拓扑和基本原理,推导了最小有功注入策略,分析了DVR的补偿能力和负载功率因数的关系,并设计了合适的控制系统。仿真结果表明,新型DVR可以处理更严重和更长时间的电压跌落,大大减少了DVR的有功注入。展开更多
A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the pow...A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the power dissipation,and keep a tolerable noise performance.Under a 3.3V supply voltage,the LA core achieves a gain of 50-dB with a power consumption below 40mW.The measured input sensitivity of the amplifier is better than 5m V _ pp .It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less.The chip area is only 0.70mm×0.70mm.According to the measurement results,this IC is expected to work at the standard bit rate levels of 2.5,3.125,and 5Gb/s.展开更多
文章根据并联同步开关电感收集(parallel synchronized switch harvesting on inductor,P-SSHI)技术,提出一种自供电的压电能量收集系统,实现了在低激励环境下的系统启动和电压输出功能,并基于压电材料分离电极理论设计冷启动电路。该...文章根据并联同步开关电感收集(parallel synchronized switch harvesting on inductor,P-SSHI)技术,提出一种自供电的压电能量收集系统,实现了在低激励环境下的系统启动和电压输出功能,并基于压电材料分离电极理论设计冷启动电路。该系统采用带有有源二极管的P-SSHI整流电路代替传统的整流结构,以减少整流过程的能量损耗,能够在动态范围内调节输出电压,实现多输出负载的功能。基于0.18μm CMOS工艺仿真结果表明,该系统的电压翻转效率达到85%,输出功率是采用传统整流电路的5.8倍,同时能够产生1.2、1.8 V 2种电压,用于不同负载供电。该自供电能量收集系统可用于解决物联网无线传感器网络节点的自供电问题。展开更多
This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and...This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and noise optimization are used in the design of a trans-impedance amplifier,which overcomes the problem of inadequate bandwidth caused by the large parasitical capacitor of the CMOS photodiode. Experimental results indicate that with a parasitical capacitance of 2pF,this circuit works at 1.25Gb/s. A clear eye diagram is obtained with an input optical signal of - 17dBm. With a power supply of 3.3V, the front-end amplifier consumes 122mW and provides a 660mV differential output.展开更多
文摘基于最小有功注入策略,提出一种新型的动态电压恢复器(dynamic voltage restorer,DVR)结构,其主要结构由基本的级联H桥逆变器和并联的晶闸管开关电感组成。文章分析了新型DVR的电路拓扑和基本原理,推导了最小有功注入策略,分析了DVR的补偿能力和负载功率因数的关系,并设计了合适的控制系统。仿真结果表明,新型DVR可以处理更严重和更长时间的电压跌落,大大减少了DVR的有功注入。
文摘A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the power dissipation,and keep a tolerable noise performance.Under a 3.3V supply voltage,the LA core achieves a gain of 50-dB with a power consumption below 40mW.The measured input sensitivity of the amplifier is better than 5m V _ pp .It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less.The chip area is only 0.70mm×0.70mm.According to the measurement results,this IC is expected to work at the standard bit rate levels of 2.5,3.125,and 5Gb/s.
文摘文章根据并联同步开关电感收集(parallel synchronized switch harvesting on inductor,P-SSHI)技术,提出一种自供电的压电能量收集系统,实现了在低激励环境下的系统启动和电压输出功能,并基于压电材料分离电极理论设计冷启动电路。该系统采用带有有源二极管的P-SSHI整流电路代替传统的整流结构,以减少整流过程的能量损耗,能够在动态范围内调节输出电压,实现多输出负载的功能。基于0.18μm CMOS工艺仿真结果表明,该系统的电压翻转效率达到85%,输出功率是采用传统整流电路的5.8倍,同时能够产生1.2、1.8 V 2种电压,用于不同负载供电。该自供电能量收集系统可用于解决物联网无线传感器网络节点的自供电问题。
文摘This paper presents a low noise, 1.25Gb/s and 124dBΩ front-end amplifier that is designed and fabricated in 0.25μm CMOS technology for optical communication applications. Active inductor shunt peaking technology and noise optimization are used in the design of a trans-impedance amplifier,which overcomes the problem of inadequate bandwidth caused by the large parasitical capacitor of the CMOS photodiode. Experimental results indicate that with a parasitical capacitance of 2pF,this circuit works at 1.25Gb/s. A clear eye diagram is obtained with an input optical signal of - 17dBm. With a power supply of 3.3V, the front-end amplifier consumes 122mW and provides a 660mV differential output.
