本文结合实际研发要求,对基于USB2.0的数字音频编解码片上系统的可测试性设计(DFT)策略进行了研究。该系统采用UMC 0.13μm CMOS工艺,集成SPRAM、DPRAM、ROM、上电复位单元POR(Power On Reset)、降压转换器LDO(Low Drop Out regulator)...本文结合实际研发要求,对基于USB2.0的数字音频编解码片上系统的可测试性设计(DFT)策略进行了研究。该系统采用UMC 0.13μm CMOS工艺,集成SPRAM、DPRAM、ROM、上电复位单元POR(Power On Reset)、降压转换器LDO(Low Drop Out regulator)、锁相环PLL(Phase Locked Loop)、电熔丝盒(e-fuse box)、ADC、USB焊盘等模块。本文采用JTAG(Joint Test Action Group)和焊盘控制逻辑PCL(Pad Control Logic)进行测试控制,使得所有模块可测试。扫描链测试采用多种优化策略,故障覆盖率达到98.06%,满足系统设计要求。存储器内建自测试(MBIST),采用并行测试和串行调试策略,将所有存储器测试时间压缩为单块最大容量存储器的测试时间。电熔丝测试控制采用状态机和编程加速逻辑,简化了测试接口,并消除了冗余的编程时间(0%～100%)。本文的各种可测试性设计策略在实际产品中已经得到验证,可广泛应用于复杂的片上系统(SoC)的设计,研究结论具有一定的应用参考价值。展开更多
The studied sample is a metallic glass in Fe-Si-B system. It is developed with the nominal composition of Fe735-Cu1-Ta3-Si13.5-B9 by single-roller melt spinning technique in air. The dielectric constant and loss facto...The studied sample is a metallic glass in Fe-Si-B system. It is developed with the nominal composition of Fe735-Cu1-Ta3-Si13.5-B9 by single-roller melt spinning technique in air. The dielectric constant and loss factor have been measured both for as cast and annealed samples using Agilent Impedance analyzer. They are found to decrease with frequency up to 10 MHz and remain constant afterwards. The decrease of dielectric constant and loss factor with frequency is due to ceasing of orientational polarizability. Their constancy is owing to presence of only electronic contribution to its polarizability above 10 MHz. Three distinct regions （1-4 MHz, 4-10 MHz and 10 MHz-1 GHz） also noticed from its frequency dependence, which might make it useful in switching and sensor devices. The temperature dependence of dielectric constant and loss factor maintain inverse relationship： （1） dielectric constant increases, and （2） loss factor decreases with annealing temperature for structural relaxation due to thermal agitation.展开更多
A 1 kbit antifuse one time programmable(OTP) memory IP,which is one of the non-volatile memory IPs,was designed and used for power management integrated circuits(ICs).A conventional antifuse OTP cell using a single po...A 1 kbit antifuse one time programmable(OTP) memory IP,which is one of the non-volatile memory IPs,was designed and used for power management integrated circuits(ICs).A conventional antifuse OTP cell using a single positive program voltage(VPP) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time,securing the reliability of medium voltage(VM) devices that are thick gate transistors.A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield drop.For the newly proposed cell,a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the antifuse.The layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek's 0.18 μm Bipolar-CMOS-DMOS(BCD) process is 567.9 μm×205.135 μm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.展开更多
文摘本文结合实际研发要求,对基于USB2.0的数字音频编解码片上系统的可测试性设计(DFT)策略进行了研究。该系统采用UMC 0.13μm CMOS工艺,集成SPRAM、DPRAM、ROM、上电复位单元POR(Power On Reset)、降压转换器LDO(Low Drop Out regulator)、锁相环PLL(Phase Locked Loop)、电熔丝盒(e-fuse box)、ADC、USB焊盘等模块。本文采用JTAG(Joint Test Action Group)和焊盘控制逻辑PCL(Pad Control Logic)进行测试控制,使得所有模块可测试。扫描链测试采用多种优化策略,故障覆盖率达到98.06%,满足系统设计要求。存储器内建自测试(MBIST),采用并行测试和串行调试策略,将所有存储器测试时间压缩为单块最大容量存储器的测试时间。电熔丝测试控制采用状态机和编程加速逻辑,简化了测试接口,并消除了冗余的编程时间(0%～100%)。本文的各种可测试性设计策略在实际产品中已经得到验证,可广泛应用于复杂的片上系统(SoC)的设计,研究结论具有一定的应用参考价值。
文摘The studied sample is a metallic glass in Fe-Si-B system. It is developed with the nominal composition of Fe735-Cu1-Ta3-Si13.5-B9 by single-roller melt spinning technique in air. The dielectric constant and loss factor have been measured both for as cast and annealed samples using Agilent Impedance analyzer. They are found to decrease with frequency up to 10 MHz and remain constant afterwards. The decrease of dielectric constant and loss factor with frequency is due to ceasing of orientational polarizability. Their constancy is owing to presence of only electronic contribution to its polarizability above 10 MHz. Three distinct regions （1-4 MHz, 4-10 MHz and 10 MHz-1 GHz） also noticed from its frequency dependence, which might make it useful in switching and sensor devices. The temperature dependence of dielectric constant and loss factor maintain inverse relationship： （1） dielectric constant increases, and （2） loss factor decreases with annealing temperature for structural relaxation due to thermal agitation.
基金Work supported by the Second Stage of Brain Korea 21 Projectssupported by Changwon National University in 2009-2010
文摘A 1 kbit antifuse one time programmable(OTP) memory IP,which is one of the non-volatile memory IPs,was designed and used for power management integrated circuits(ICs).A conventional antifuse OTP cell using a single positive program voltage(VPP) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time,securing the reliability of medium voltage(VM) devices that are thick gate transistors.A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield drop.For the newly proposed cell,a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the antifuse.The layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek's 0.18 μm Bipolar-CMOS-DMOS(BCD) process is 567.9 μm×205.135 μm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.
