低温低电耗低浓度多稀土镀铬添加剂

低温低电耗低浓度多稀土镀铬添加剂该添加剂系针对普通高铬镀铬工艺以及无稀土型、单一稀土型、混合稀土型镀铬添加剂所存在的问题，采用“多稀土纯品优化组合法”开发的一种宽温、宽浓度（尤其适用低温、低浓度）、低电耗镀铬的新一代镀铬添加剂。该添加剂采用吸氢剂、导...

A 5mW 1.8V Low Over-Sampling Ratio ΣΔ Modulator with 81dB Dynamic Range

This work demonstrates that the ΣΔ modulator with a low oversampling ratio is a viable option for the high-resolution digitization in a low-voltage environment.Low power dissipation is achieved by designing a low-OSR modulator based on differential cascade architecture,while large signal swing maintained to achieve a high dynamic range in the low-voltage environment.Operating from a voltage supply of 1.8V,the sixth-order cascade modulator at a sampling frequency of 4-MHz with an OSR of 24 achieves a dynamic range of 81dB for a 80-kHz test signal,while dissipating only 5mW.

A 71mW 8b 125MSample/s A/D Converter

A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.

Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies

Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed. Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE. The simulation results show that the proposed circuits effectively lower the active power, reduce the total leakage current, and enhance speed under similar noise immunity conditions. The active power of the two proposed circuits can be reduced by up to 8. 8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage. At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4% ,respectively. Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.

Synthesis Scheme for Low Power Designs Under Timing Constraints

To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.

Design of an Analog Front End for Passive UHF RFID Transponder IC

This paper introduces a high-performance analog front end for a passive UHF RFID transponder IC, which is compatible with the ISO/IEC 18000-6B standard,operating at the 915MHz ISM band with a total supply current consumption less than 8μA. There are no external components, except for the antenna. The passive IC＇s power supply is taken from the energy of the received RF electromagnetic field with the help of a Schottky diode rectifier. The RFID analog front end includes a local oscillator, clock generator, power on reset circuit, matching network and backscatter,rectifier,regulator, and AM demodulator. The IC, whose reading distance is more than 3m,is fabricated with a Chartered 0.35μm two-poly four-metal CMOS process with Schottky diodes and is EEPROM supported. The core size is 300μm × 720μm.

辊压机联合粉磨系统和半终粉磨系统的应用比较

辊压机联合粉磨系统和半终粉磨系统在同一公司应用,比较结果发现:半终粉磨系统装机容量大,投资多,产量高,电耗低,水泥需水量有所增加;辊压机对物料的适应性相对较差,设备磨损快,操作较为复杂等。只有加强调整与维护,才能确保系统稳定,提升系统产能和效率。联合粉磨系统操作相对简单,水泥质量稳定,但电耗高于半终粉磨系统。

An Ultra-Low-Power Embedded EEPROM for Passive RFID Tags

An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.

Analysis and Design of a Low-Cost RFID Tag Analog Front-End

A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFID tags. The read distance is as far as 22cm.

A Low Voltage,Low Power RF/Analog Front-End Circuit for Passive UHF RFID Tags

This paper presents a low voltage, low power RF/analog front-end circuit for passive ultra high frequency （UHF） radio frequency identification （RFID） tags. Temperature compensation is achieved by a reference generator using sub-threshold techniques. The chip maintains a steady system clock in a temperature range from - 40 to 100℃. Some novel building blocks are developed to save system power consumption,including a zero static current power-on reset circuit and a voltage regulator. The RF/analog front-end circuit is implemented with digital base-band and EEPROM to construct a whole tag chip in 0. 18μm CMOS EEPROM technology without Schottcky diodes. Measured results show that the chip has a minimum supply voltage requirement of 0.75V. At this voltage, the total current consumption of the RF/analog frontend circuit is 4.6μA.

A 1V,156.7μW,65.9dB Rail-to-Rail Operational Amplifier by Means of Negative Resistance Load and Replica-Amplifier Gain Enhancement

A low-voltage, low-power, and high-gain rail-to-rail operational amplifier （OpAmp） is presented. The replica-amplifier gain enhancement technique is applied to improve the DC gain of the amplifier, which does not degrade the output swing and is very suitable for low-voltage applications. In a 0. 18/μm standard CMOS process,a 1V OpAmp with rail-to-rail output is designed. For a load capacitance of 5 pF,simulation by HSPICE shows that this OpAmp achieves an effective open-loop DC gain of 65. 9dB,gain bandwidth of 70.28 MHz,and phase margin of 50 with a quiescent power dissipation of 156.7μW.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification （RFID） transponder IC, which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor. The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency. An analytical model of the voltage multiplier, comparison with other charge pumps, simulation results, and chip testing results are presented.

水泥辊压机终粉磨工艺的实践

在水泥粉磨工艺中,辊压机承担着预粉磨的作用,为减少水泥过粉磨现象,近年来水泥工艺改造上采用了半终粉磨技术,将辊压机碾压的成品选粉入库.结合半终粉磨系统的特点,在该系统上进一步改造、优化以实现将辊压机作为终端粉磨,在保证水泥性能的前提下,探讨节能降耗的思路,并取得成功.

LOW-POWER LVDS I/O INTERFACE FOR ABOVE 2GB/S-PER-PIN OPERATION

Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.

A Passive Low-Pass Filter on Low-Loss Substrate

The loss mechanisms of different passive devices （on-chip inductors and capacitors） on different substrates are analyzed and compared. OPS （oxidized porous silicon） and HR （high-resistivity） substrates are used as low-loss substrates for on-chip planar LPF （low pass filter） fabrication. For the study of substrate loss, a planar coil inductor is also designed. Simulation results show that Q （the quality factor） of the inductor on both substrates is over 20. Measurements of the LPF on OPS substrate give a - 3dB bandwidth of 2.9GHz and a midband insertion loss of 0.87dB at 500MHz. The LPF on HR substrate gives a - 3dB bandwidth of 2.3GHz and a midband insertion loss of 0.42dB at 500MHz.

A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic

Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.

DESIGN OF TERNARY COUNTER BASED ON ADIABATIC DOMINO CIRCUIT

By researching the ternary counter and low power circuit design method, a novel design of low power ternary Domino counter on switch-level is proposed. Firstly, the switch-level structure expression of ternary loop operation circuit with enable pin is derived according to the switch-signal theory, and the one bit ternary counter is obtained combining the ternary adiabatic Domino literal operation circuit and buffer. Then the switch-level structure expression of enable signal circuit is derived, and the four bits ternary counter is obtained by cascade connection. Finally, the circuit is simulated by Spice tool and the output waveforms transform in proper order indicating that the logic function is correct. The energy consumption of the four bits ternary adiabatic Domino counter is 63% less than the conventional Domino counterpart.

High permittivity and low dielectric loss analysis of lead free Sr_(1-x)La_x(Ti_(0.5) Fe_(0.5))O_3

The structural and electrical properties of lead free Srx-xLax（Tio.sFeo.5）O3 （SLTFO） prepared by standard solid state reaction technique were studied. The X-ray diffraction analysis confirmed the formation of a single-phase cubic perovskite structure. The compositional dependence of lattice constant, density and microstructural studies show that they vary significantly with La3＋ content. When measured at 10 kHz, all the compositions of SLTFO at room temperature exhibit a high permittivity （about 104） and low dielectric loss （about 10-3）. SLTFO also display minimum dielectric loss within the lower and higher limits of frequency, indicating that the samples are of good quality. It is concluded from the calculated ac conductivity that the conduction is due to mixed polarons hopping. The complex impedance plot exhibits a tendency of forming a single semicircular arc for all compositions, which implies a dominance of grain boundary resistance on the impedance. Impedance parameters were determined by fitting the experimental data with Cole-Cole empirical formula. The results of the present experiment indicate that the lead free SLTFO materials with higher permittivity and lower dielectric loss have possible practical applications.

Low-Power Digital Circuit Design with Triple-Threshold Voltage

Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.