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基于最优神经网络的电路测试方法研究
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作者 潘中良 张光昭 《中山大学学报(自然科学版)》 CAS CSCD 北大核心 1999年第6期29-33,共5页
在数字电路最优神经网络模型的基础上,研究基于该模型的电路测试生成方法.首先获得了多输入基本门电路的最优神经网络能量函数的一般表达式,然后对这种测试方法的原理、实现步骤、以及加速测试的措施等进行了详细研究.结果表明以最优神... 在数字电路最优神经网络模型的基础上,研究基于该模型的电路测试生成方法.首先获得了多输入基本门电路的最优神经网络能量函数的一般表达式,然后对这种测试方法的原理、实现步骤、以及加速测试的措施等进行了详细研究.结果表明以最优神经网络模型为基础的电路测试方法在测试生成的速度方面快于其它类似方法,如基于Hopfield神经网络的电路测试生成,具有较好的应用潜力. 展开更多
关键词 数字电路 最优神经网络 能量函数 电路测试法
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Research of the test generation algorithm based on search state dominance for combinational circuit
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作者 吴丽华 俞红娟 +1 位作者 王轸 马怀俭 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2006年第1期62-64,共3页
On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the... On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the E-frontier (evaluation frontier), we can prove that this algorithm can terminate unnecessary searching step of test pattern earlier than the EST algorithm through some examples, so this algorithm can reduce the time of test generation. The test patterns calculated can detect faults given through simulation. 展开更多
关键词 E-frontier test generation combinational circuit
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The structure-based multi-fault test generation algorithm for combinational circuit
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作者 商庆华 吴丽华 项傅佳 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2006年第4期452-454,共3页
In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns o... In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns one tithe, so faults detection is very convenient. By simulation, the smallest test patterns set can be obtained and faults coverage rate is 100%. 展开更多
关键词 combinational circuit test generation the smallest test patterns set
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A new approach to test generation for combinational circuits
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作者 赵春晖 侯艳丽 +1 位作者 胡佳伟 兰海燕 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2009年第1期61-65,共5页
Aimed at the generation of high-quality test set in the shortest possible time, the test generation for combinational circuits (CC) based on the chaotic particle swarm optimization (CPSO) algorithm is presented ac... Aimed at the generation of high-quality test set in the shortest possible time, the test generation for combinational circuits (CC) based on the chaotic particle swarm optimization (CPSO) algorithm is presented according to the analysis of existent problems of CC test generation, and an appropriate CPSO algorithm model has been constructed. With the help of fault simulator, the test set of ISCAS' 85 benchmark CC is generated using the CPSO, and some techniques are introduced such as half-random generation, and simulation of undetected fauhs.with original test vector, and inverse test vector. Experimental results show that this algorithm can generate the same fault coverage and small-size test set in short time compared with other known similar methods, which proves that the proposed method is applicable and effective. 展开更多
关键词 test generation combinational circuits: particle swarm ootimization: chaotic ontimization
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