基于并口的VPI转换器及其应用

VPI接口的工程绘图仪在地震资料与测井资料数据处理中使用广泛,但它们无法在微机WINDOWS操作系统下联机驱动。基于微机并行接口,通过设计一外置VPI接口转换器,配合驱动程序,实现了在多种处理平台下WINDOWS2000/XP驱动各种VPI接口的工程绘图仪。VPI接口转换器具有结构简单、输出快捷、经济实用等优点。

新型AD/DA转换器集成电路

本文介绍的4种新型数据转换器集成电路：ADC083000、AD7980、MAX1302、LTC2641。数据转换器包括ADC和DAC两大类，ADC是“Analog to Digital Converters”的缩写，中文名称是模数转换器，DAC是“Digital to Analog Converters”的缩写，中文名称是数模转换器，此处的“数”是指“数字信号”，“模”是指“模拟信号”。我们已经开始进入数字化时代，数字化技术使参量的存储、处理、还原、转化、借用变得非常容易且不易产生额外的失真，不过通常我们所能感知的参量都是模拟的，如声音、图像、光线、温度、疼痛、压力、气味等，数据转换器在模拟与数字之间的转换起着重要的桥梁作用。实际的应用系统中，为了将模拟量转化为数字量，传感器是必须的，如数码相机中的CCD器件，温度传感器、压力传感器等；为了将数字量转化为模拟量，最终模拟执行机构也是必须的，大多根据实际用途来命名，如荧光屏是显示图像的，扬声器是发出声音的，继电器用作开关，这些器件作为一个系统的执行机构，将数字信息变为我们可以实际感知的信息——模拟参量。

10Gbit/s甚短距离传输系统接收模块研究

本文研究了符合OIF-VSR4-01.0规范的甚短距离(VSR)并行光传输系统转换器集成电路,实现了接收部分转换器集成电路中帧同步、8B/10B解码、12路通道去斜移、检错纠错等模块的设计。在Altera的StratixGX系列的FPGA上实现了接收部分转换器集成电路。仿真分析的结果表明所设计的各个模块能正确的实现接收部分转换器集成电路的功能,给出了仿真结果。

变压器局部放电超高频检测传感器设计的探讨

针对变压器的运行和结构特点,分析了用于变压器局部放电超高频信号检测的传感器设计要求,介绍了双臂阿基米德平面螺旋天线的基本原理和设计方法,分析了天线馈电的基本原理,提出了应用印刷电路对称转换器对天线进行馈电的设计思想。

200Ms/s 177mW 8bit Folding and Interpolating CMOS A/D Converter

A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.

A Novel Sampling Switch Suitable for Low-Voltage Analog-to-Digital Converters

A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.

Analysis and design of high linearity current reference for current mode circuits

A complementary metal-oxide-semiconductor transistor （CMOS） voltage-to-current（VTC）converter with high linearity for current-mode analog and digital integrated circuits is described. A high gain operational amplifier （OPA） is utilized to form negative feedback. A proportional to absolute temperature （PTAT） current reference with transistors operated in a weak inversion is used as the bias circuit. The resistor and the OPA nonlinearity behavior are analyzed in detail. By optimizing parameters in OPA and adopting a small voltage coefficient polysilicon resistor as a linear device, a high linearity is achieved. The circuit is implemented in a standard 0. 6 μm CMOS technology. The low frequency gain of the OPA exceeds 90 dB. The test results indicate that the total harmonic distortion （THD）is 0. 000 2%. The common-mode input linearity range is 0 to 2. 6 V. Correspondingly, the output current range is 50 to 426μA. The sensitivity of the PTAT current reference to Vdd is approximately 0. 021 7. The chip consumes a power of less than 1.3 mW for a 5 V supply, and occupies an area of 0. 112 mm^2.

Multi-mode controller IC for soft-switched flyback converter with high efficiency over the entire load range

This paper presents a multi-mode control scheme for a soft-switched flyback converter to achieve high efficiency and excellent load regulation over the entire load range. At heavy load, critical conduction mode with valley switching (CCMVS) is employed to realize soft switching so as to reduce turn-on loss of power switch as well as conducted electromagnetic interference (EMI). At light load, the converter operates in discontinuous conduction mode (DCM) with valley switching and adaptive off-time control (AOT) to limit the switching frequency range and maintain load regulation. At extremely light load or in standby mode, burst mode operation is adopted to provide low power consumption through reducing both switching frequency and static power dissipation of the controller. The multi-mode control is implemented by an oscillator whose pulse duration is adjusted by output feedback. An accurate valley switching control circuit guarantees the minimum turn-on voltage drop of power switch. The pro-totype of the controller IC was fabricated in a 1.5-μm BiCMOS process and applied to a 310 V/20 V, 90 W flyback DC/DC converter circuitry. Experimental results showed that all expected functions were realized successfully. The flyback converter achieved a high efficiency of over 80% from full load down to 2.5 W, with the maximum reaching 88.8%, while the total power consumption in standby mode was about 300 mW.

THE DESIGN OF HIGH PERFORMANCE LINEAR TRANSCONDUCTOR

An improved structure of linear transconductor is presented in this paper. It is analyzed in theory and simulated with Spectre based on 0.25μm CMOS process. The simulation results show that the differential input voltage of the proposed transconductor is 4.0Vpp(peak to peak), whereas the differential input voltage of the existing source degeneration structure is 2.2Vpp, when their nonlinear errors are required to be less than 0.15%.

Synchronization analysis on cascaded multilevel converters with distributed control

Cascaded multilevel converters built with integrated modules have many advantages such as increased power density,flexible distributed control,multi-functionality,increased reliability and short design cycles.However,the system performance will be affected due to the synchronization errors among each integrated modules.This paper analyzes the impact of the three kinds of synchronization errors on the whole system performance,as well as detailed synchronization implementation.Some valuable conclusions are derived from the theoretical analysis,simulations and experimental results.

A novel design of power management integrated circuit with 90 plus efficiency used in AC/DC converter

Recently, resonant AC/DC converter has been accepted by the industry. However, the efficiency will be decreased at light load. So, a novel topology with critical controlling mode combined with resonant ones is proposed in this paper. The new topology can correspond to a 90 plus percent of power converting. So,a novel topology of an state of art integrated circuit, which can be used as power management circuit, has been designed based on the above new topology. A simulator which is specifically suitable for the power controller has been founded in this work and it has been used for the simulation of the novel architecture and the proposed integrated circuit.

Inductor Losses Estimation in DC-DC Converters by Means of Averaging Technique

A suitable inductor modeling for power electronic DC-DC converters is presented in this paper. It is developed with the aim of improving inductor losses estimation achievable by averaged models, which inherently neglect inductor current ripple. In order to account for its contribution to the overall inductor losses, an appropriate parallel resistance is thus enclosed into the inductor model, whose value should be chosen in accordance with the DC-DC converter operating conditions. This allows the development of improved averaged models of DC-DC converters, especially in terms of power losses estimation. The effectiveness of the proposed modeling approach has been validated through a simulation study, which refers to the case of a boost DC-DC converter and is performed by means of a suitable circuit simulator designed for rapid modelling of switching power systems （SIMetrix/SIMPLIS）.

High Speed Column-Parallel CDS/ADC Circuit with Nonlinearity Compensation for CMOS Image Sensors

A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.

单周控制的单相交流斩波调压电路

阐述了单周控制用于单相电压交流斩波AC/AC转换器工作原理,并利用Matlab/Simulink软件对并联型转换器Buck电路建模并进行仿真,给出了电阻性负载稳态及突变情况下的仿真结果,证明在原理上是可行的。

CsPbBrI perovskites with low energy loss for high-performance indoor and outdoor photovoltaics

Over the years,the efficiency of inorganic perovskite solar cells(PSCs)has increased at an unprecedented pace.However,energy loss in the device has limited a further increase in efficiency and commercialization.In this work,we used(NH4)2C2O4·H2O to treat CsPbBrI2 perovskite film during spin-coating.The CsPbBrI2 underwent secondary crystallization to form high quality films with micrometer-scale and low trap density.(NH4)2C2O4·H2O treatment promoted charge transfer capacity and reduced the ideal factor.It also dropped the energy loss from 0.80 to 0.64 eV.The resulting device delivered a power conversion efficiency(PCE)of 16.55%with an open-circuit voltage(Voc)of 1.24 V,which are largely improved compared with the reference device which exhibited a PCE of 13.27%and a Voc of 1.10 V.In addition,the optimized treated device presented a record indoor PCE of 28.48%under a fluorescent lamp of 1000 lux,better than that of the reference device(19.05%).

Simulation of high conversion efficiency and open-circuit voltages of α-si/poly-silicon solar cell

The P+ α-Si /N+ polycrystalline solar cell is molded using the AMPS-1D device simulator to explore the new high efficiency thin film poly-silicon solar cell. In order to analyze the characteristics of this device and the thickness of N+ poly-silicon, we consider the impurity concentration in the N+ poly-silicon layer and the work function of transparent conductive oxide (TCO) in front contact in the calculation. The thickness of N+ poly-silicon has little impact on the device when the thickness varies from 20 μm to 300 μm. The effects of impurity concentration in polycrystalline are analyzed. The conclusion is drawn that the open-circuit voltage (Voc) of P+ α-Si /N+ polycrystalline solar cell is very high, reaching 752 mV, and the conversion efficiency reaches 9.44%. Therefore, based on the above optimum parameters the study on the device formed by P+ α-Si/N+ poly-silicon is significant in exploring the high efficiency poly-silicon solar cell.