A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency div...A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.展开更多
An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,us...An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,used in the DSCRL adiabatic circuit.Although the 4 phase power clock is simpler,the DSCRL adiabatic circuit still shows good performance and high efficiency of energy transfer and recovery.This conclusion has been proved by the result of the HSPICE simulation using the 0 6μm CMOS technology.展开更多
A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given....A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.展开更多
First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked...First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.展开更多
Oscillator IC technique is developed by combining injecting synchronization technique with a ring VCO.Using the technique,a novel 2 488GHz of monolithical integrated injected synchronized ring VCO (ISRVCO) is realize...Oscillator IC technique is developed by combining injecting synchronization technique with a ring VCO.Using the technique,a novel 2 488GHz of monolithical integrated injected synchronized ring VCO (ISRVCO) is realized in a standard 0 25μm CMOS process.The ISRVCO is characterized by the following performances: -100dBc /Hz@1MHz at free running frequency,-91 7dBc/Hz@10kHz when injection is locked.With the 3 3V of power supply,the tuning range is 150MHz and the locking range is 100MHz with 50m V p p signal injection.展开更多
A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a...A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a clock and data recovery＇ circuit （CDR）. Each sub-model is constructed based on the architecture of a circuit. The noise and jitter in each block such as shot noise, thermal noise, deterministic and random jitter are also considered. The performance of the whole receiver can be evaluated by the simulation of the behavior model, which is faster than the ordinary circuit model and more accurate than the analytical model. The whole model is implemented with C ＋＋ and simulated in Microsoft Visual C ＋＋ 6. 0. Using the Monte Carlo method, the EPON receiver is simulated. The simulation results show a good agreement with experimental ones.展开更多
Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also propose...Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.展开更多
In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at h...In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.展开更多
This paper constructs the probability model of the multi-valued KM_1M_2 clock controlled generator,and discusses the probability distributing,homogeneous Markov property,ergodic property,strict placidity,numeral chara...This paper constructs the probability model of the multi-valued KM_1M_2 clock controlled generator,and discusses the probability distributing,homogeneous Markov property,ergodic property,strict placidity,numeral character and the property of large numbers of the random variables with this kind of output sequence.It gets the probability formula of the coincidence of the output sequence with the input sequence,and gives important reference to the design and analysis of the multi-valued key stream clock controlled generator in cryptography.展开更多
A two-way satellite time and frequency transfer(TWSTFT) device equipped in the BeiDou navigation satellite system(BDS)can calculate clock error between satellite and ground master clock. TWSTFT is a real-time method w...A two-way satellite time and frequency transfer(TWSTFT) device equipped in the BeiDou navigation satellite system(BDS)can calculate clock error between satellite and ground master clock. TWSTFT is a real-time method with high accuracy because most system errors such as orbital error, station position error, and tropospheric and ionospheric delay error can be eliminated by calculating the two-way pseudorange difference. Another method, the multi-satellite precision orbit determination(MPOD)method, can be applied to estimate satellite clock errors. By comparison with MPOD clock estimations, this paper discusses the applications of the BDS TWSTFT clock observations in satellite clock measurement, satellite clock prediction, navigation system time monitor, and satellite clock performance assessment in orbit. The results show that with TWSTFT clock observations, the accuracy of satellite clock prediction is higher than MPOD. Five continuous weeks of comparisons with three international GNSS Service(IGS) analysis centers(ACs) show that the reference time difference between BeiDou time(BDT) and golbal positoning system(GPS) time(GPST) realized IGS ACs is in the tens of nanoseconds. Applying the TWSTFT clock error observations may obtain more accurate satellite clock performance evaluation in the 104 s interval because the accuracy of the MPOD clock estimation is not sufficiently high. By comparing the BDS and GPS satellite clock performance, we found that the BDS clock stability at the 103 s interval is approximately 10.12, which is similar to the GPS IIR.展开更多
We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multipli...We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two's complement multiplier-accumulator(MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor(CMOS) logic.展开更多
文摘A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.
文摘An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,used in the DSCRL adiabatic circuit.Although the 4 phase power clock is simpler,the DSCRL adiabatic circuit still shows good performance and high efficiency of energy transfer and recovery.This conclusion has been proved by the result of the HSPICE simulation using the 0 6μm CMOS technology.
文摘A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.
基金Supported by the National Natural Science Foundation of China (No. 60273093)the Natural Science Foundation of Zhejinag Province(No. Y104135) the Student Sci-entific Research Foundation of Ningbo university (No.C38).
文摘First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.
文摘Oscillator IC technique is developed by combining injecting synchronization technique with a ring VCO.Using the technique,a novel 2 488GHz of monolithical integrated injected synchronized ring VCO (ISRVCO) is realized in a standard 0 25μm CMOS process.The ISRVCO is characterized by the following performances: -100dBc /Hz@1MHz at free running frequency,-91 7dBc/Hz@10kHz when injection is locked.With the 3 3V of power supply,the tuning range is 150MHz and the locking range is 100MHz with 50m V p p signal injection.
文摘A behavior model for the receiver of the Ethernet passive optical network（EPON） is presented. The model consists of a fiber, a photodetector, a transimpedance amplifier （TIA） followed by a limiting amplifier and a clock and data recovery＇ circuit （CDR）. Each sub-model is constructed based on the architecture of a circuit. The noise and jitter in each block such as shot noise, thermal noise, deterministic and random jitter are also considered. The performance of the whole receiver can be evaluated by the simulation of the behavior model, which is faster than the ordinary circuit model and more accurate than the analytical model. The whole model is implemented with C ＋＋ and simulated in Microsoft Visual C ＋＋ 6. 0. Using the Monte Carlo method, the EPON receiver is simulated. The simulation results show a good agreement with experimental ones.
文摘Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.
基金the Natural Science Foundation of Hei- longjiang Province, China (F2004-17).
文摘In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.
基金Supported by the Computer Network and Information Security Foundation of Ministry of Education Laboratory(20040108)
文摘This paper constructs the probability model of the multi-valued KM_1M_2 clock controlled generator,and discusses the probability distributing,homogeneous Markov property,ergodic property,strict placidity,numeral character and the property of large numbers of the random variables with this kind of output sequence.It gets the probability formula of the coincidence of the output sequence with the input sequence,and gives important reference to the design and analysis of the multi-valued key stream clock controlled generator in cryptography.
基金supported by the National Natural Sciences Foundation of China(Grant No.41574029)Youth Innovation Promotion Association CAS(Grant No.2016242)
文摘A two-way satellite time and frequency transfer(TWSTFT) device equipped in the BeiDou navigation satellite system(BDS)can calculate clock error between satellite and ground master clock. TWSTFT is a real-time method with high accuracy because most system errors such as orbital error, station position error, and tropospheric and ionospheric delay error can be eliminated by calculating the two-way pseudorange difference. Another method, the multi-satellite precision orbit determination(MPOD)method, can be applied to estimate satellite clock errors. By comparison with MPOD clock estimations, this paper discusses the applications of the BDS TWSTFT clock observations in satellite clock measurement, satellite clock prediction, navigation system time monitor, and satellite clock performance assessment in orbit. The results show that with TWSTFT clock observations, the accuracy of satellite clock prediction is higher than MPOD. Five continuous weeks of comparisons with three international GNSS Service(IGS) analysis centers(ACs) show that the reference time difference between BeiDou time(BDT) and golbal positoning system(GPS) time(GPST) realized IGS ACs is in the tens of nanoseconds. Applying the TWSTFT clock error observations may obtain more accurate satellite clock performance evaluation in the 104 s interval because the accuracy of the MPOD clock estimation is not sufficiently high. By comparing the BDS and GPS satellite clock performance, we found that the BDS clock stability at the 103 s interval is approximately 10.12, which is similar to the GPS IIR.
基金supported by the National Natural Science Foundation of China (No. 60776022)the Science and Technology Fund of Zhejiang Province (No. 2008C21166)+3 种基金the Key Scientific Research Fund of the Department of Education of Zhejiang Province (No. 20061666)the Professor Fund (No. JSL2007001)the Scientific Research Fund (No. XK0610030)the K. C. Wong Magna Fund in Ningbo University, China
文摘We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two's complement multiplier-accumulator(MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor(CMOS) logic.
