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一种高分辨低杂散频率合成方法 被引量:1
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作者 高媛 张佳俊 韩文革 《电测与仪表》 北大核心 2019年第21期36-40,69,共6页
针对频率合成器分辨率和范围之间的矛盾及影响频率稳定度的相位噪声问题,提出一种基于两级小数分频锁相环的频率合成方法,该方法以前级小数分频锁相环实现频率高分辨;在后级小数分频锁相环对输出信号相噪抑制的基础上,实现输出频率范围... 针对频率合成器分辨率和范围之间的矛盾及影响频率稳定度的相位噪声问题,提出一种基于两级小数分频锁相环的频率合成方法,该方法以前级小数分频锁相环实现频率高分辨;在后级小数分频锁相环对输出信号相噪抑制的基础上,实现输出频率范围的扩展;通过在两级小数分频锁相环之间设计窄带锁相环滤波器对前级小数分频锁相环的噪声进行隔离,且窄带锁相环滤波器的鉴相频率根据后级小数分频锁相环分频比的小数值进行切换,实现对频率合成器的小数分频杂散的有效抑制。 展开更多
关键词 频率分辨相位噪声 小数分频杂散 窄带滤波器
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A wideband low-phase-noise LC VCO for DRM/DAB frequency synthesizer
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作者 雷雪梅 王志功 王科平 《Journal of Southeast University(English Edition)》 EI CAS 2010年第4期528-531,共4页
The wideband CMOS voltage-controlled oscillator(VCO)with low phase noise and low power consumption is presented for a DRM/DAB(digital radio mondiale and digital audio broadcasting)frequency synthesizer.In order to... The wideband CMOS voltage-controlled oscillator(VCO)with low phase noise and low power consumption is presented for a DRM/DAB(digital radio mondiale and digital audio broadcasting)frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply. 展开更多
关键词 CMOS voltage-controlled oscillator switched capacitor bank MOS varactors WIDEBAND low phase noise DRM/DAB frequency synthesizer
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可评测大多数射频和微波信号源的信号源分析仪
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《今日电子》 2004年第9期102-102,共1页
关键词 信号源分析仪 E5052A 微波信号源 相位噪声频率 瞬时频率测量
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A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications
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作者 姜亚伟 李智群 +1 位作者 舒海涌 侯凝冰 《Journal of Southeast University(English Edition)》 EI CAS 2010年第1期6-10,共5页
A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant ac... A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator(VCO)are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature(IQ)signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency(RF) complementary metal oxide semiconductor transistor (CMOS)technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs. 展开更多
关键词 phase-locked loop phase noise auto frequency calibration ZIGBEE voltage controlled oscillator
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