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抑制DDS相位舍位杂散的一种新方法 被引量:5
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作者 张少元 郭燕昌 +1 位作者 张锁敖 柳永祥 《现代雷达》 CSCD 北大核心 2001年第4期55-58,共4页
直接数字式频率合成器 (DDS)是最新的频率合成技术 ,它具有分辨率高 ,频率转换速度快等优点 ,但是杂散分量丰富。本文旨在介绍相控阵天线抑制旁瓣的几种方法 ,并利用其中的随机相位馈相法来处理相位舍位条件下的 DDS,从而降低杂散电平。
关键词 直接数字频率合成 相控阵天线 旁瓣 相位舍位 杂散
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A New High Performance FM Transmitter 被引量:1
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作者 曹政新 李学初 +3 位作者 李振 吴岳 宋树贵 熊绍珍 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第5期655-660,共6页
A new FM transmitter is reported. It adopts a fractional-N PLL synthesizer to realize the FM modulator. An extra offset current has also been applied to eliminate the effects of the mismatch in CP. The chip is fabrica... A new FM transmitter is reported. It adopts a fractional-N PLL synthesizer to realize the FM modulator. An extra offset current has also been applied to eliminate the effects of the mismatch in CP. The chip is fabricated with CSMC 0.5μm DPTM CMOS technology. Experiments show that it achieves THD≤0.08% and SNR≤ 82dB,and the maximum outband emission energy ≤ 90dBc/Hz. Furthermore,it also uses an auto frequency adjusting method to avoid tuning up the external inductances. All these merits are very suitable for FM transmission. 展开更多
关键词 FM fraction N frequency synthesizer in-band phase noise
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结合专业技术和四要素法简论如何控制高校会务演出设备成本
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作者 谈恒怀 《科技信息》 2011年第16期365-365,共1页
当前物价飞涨,CPI节节攀高的2011年,各高校面临人力、财力、物力有限的窘境,降低运营成本无疑是各高校每个部门必须面对的。尤其一些综合性大学在高等教育日益国际化的今天,高校运行成本的高低一定程度上影响着高校的竞争力。高校后勤... 当前物价飞涨,CPI节节攀高的2011年,各高校面临人力、财力、物力有限的窘境,降低运营成本无疑是各高校每个部门必须面对的。尤其一些综合性大学在高等教育日益国际化的今天,高校运行成本的高低一定程度上影响着高校的竞争力。高校后勤教职工应当如何做好部门内部优化,结合职工自身技术特长,将部门运营成本控制在一个合理范围,本文将立足于一所综合性大学会务管理部门,从技术管理者的角度利用四要素法,着手于会务、演出设备的成本消耗,从某些方面论述哪些行动可以降低运营成本。 展开更多
关键词 人机料法环 人事制度公开化 高校后勤管理 相位频率合成 相位锁相环 功率放大器 自动选讯接收 杂波干扰
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The Jitter Performance Comparison Between DLL and PLL-Based RF CMOS Oscillators
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作者 李金城 仇玉林 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2001年第10期1246-1249,共4页
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ... By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance. 展开更多
关键词 JITTER PLL DLL frequency synthesizer RF CMOS transceiver Local Oscillator(LO) Voltage Controlled Delay Line(VCDL) VCO
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A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver
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作者 贾海珑 任彤 +3 位作者 林敏 陈方雄 石寅 代伐 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第10期1968-1973,共6页
This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows ... This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well. 展开更多
关键词 PLL GPS frequency synthesizer VCO low power CMOS RF
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