A low-phase-noise and low-power crystal oscillator for RF tuner

A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.

Wideband CMOS LC VCO design and phase noise analysis

A wideband LC cross-coupled voltage controlled oscillator（VCO） is designed and realized with standard 0. 18 μm complementary metal-oxide-semiconductor（CMOS） technology. Band switching capacitors are adopted to extend the frequency tuning range, and the phase noise is optimized in the design procedure. The functional relationships between the phase noise and the transistors＇ width-length ratios are deduced by a linear time variant （LTV） model. The theoretical optimized parameter value ranges are determined. To simplify the calculation, the working region is split into several sub-ranges according to transistor working conditions. Thus, a lot of integrations are avoided, and the phase noise function upon the design variables can be expressed as simple proportion formats. Test results show that the DC current is 8.8 mA under a voltage supply of 1.8 V; the frequency range is 1.17 to 1.90 GHz, and the phase noise reaches - 83 dBc/Hz at a 10 kHz offset from the carrier. The chip size is 1. 2 mm × 0. 9 mm.

A New High Performance FM Transmitter

A new FM transmitter is reported. It adopts a fractional-N PLL synthesizer to realize the FM modulator. An extra offset current has also been applied to eliminate the effects of the mismatch in CP. The chip is fabricated with CSMC 0.5μm DPTM CMOS technology. Experiments show that it achieves THD≤0.08% and SNR≤ 82dB,and the maximum outband emission energy ≤ 90dBc/Hz. Furthermore,it also uses an auto frequency adjusting method to avoid tuning up the external inductances. All these merits are very suitable for FM transmission.

A 5-Gbit/s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS

In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.

Ultrasonic method for measuring water holdup of low velocity and high-water-cut oil-water two-phase flow

Oil reservoirs with low permeability and porosity that are in the middle and late exploitation periods in China＇s onshore oil fields are mostly in the high-water-cut production stage.This stage is associated with severely non-uniform local-velocity flow profiles and dispersed-phase concentration（of oil droplets） in oil-water two-phase flow,which makes it difficult to measure water holdup in oil wells.In this study,we use an ultrasonic method based on a transmission-type sensor in oil-water two-phase flow to measure water holdup in lowvelocity and high water-cut conditions.First,we optimize the excitation frequency of the ultrasonic sensor by calculating the sensitivity of the ultrasonic field using the finite element method for multiphysics coupling.Then we calculate the change trend of sound pressure level attenuation ratio with the increase in oil holdup to verify the feasibility of the employed diameter for the ultrasonic sensor.Based on the results,we then investigate the effects of oildroplet diameter and distribution on the ultrasonic field.To further understand the measurement characteristics of the ultrasonic sensor,we perform a flow loop test on vertical upward oilwater two-phase flow and measure the responses of the optimized ultrasonic sensor.The results show that the ultrasonic sensor yields poor resolution for a dispersed oil slug in water flow（D OS/W flow）,but the resolution is favorable for dispersed oil in water flow（D O/W flow） and very fine dispersed oil in water flow（VFD O/W flow）.This research demonstrates the potential application of a pulsed-transmission ultrasonic method for measuring the fraction of individual components in oil-water two-phase flow with a low mixture velocity and high water cut.

A 2GHz Low Power Differentially Tuned CMOS Monolithic LC-VCO

A 2GHz differentially tuned CMOS monolithic LC-VCO is designed and fabricated in a 0.18μm CMOS process. The VCO has a 16.15% tuning range （from 1. 8998 to 2. 2335GHz） through a combination of analog and digital tuning techniques （4-bit binary switch-capacitor array）. The measured phase noise is - 118.17dBc/Hz at a 1MHz offset from a 2. 158GHz carrier. With the presented improved switch,the phase noise varies no more than 3dB at different digital control bits. The phase noise changes only by about 2dB in the tuning range because of the pn-junctions as the varactors. The VCO draws a current of about 2. lmA from a 1.8V power supply and works normally with a 1.5V power supply.

Low Phase Noise Quadrature Oscillators Using New Injection Locked Technique

A low phase noise quadrature oscillator using the new injection locked technique is proposed. The incident signal is directly injected into the common-source connection of the sub-harmonic oscillator. In principle, the phase noise performance of the quadrature output is better than the sub-harmonic oscillator itself. The quadrature oscillator is implemented in a 0. 25μm CMOS process. Measurements show the proposed oscillator could achieve a phase noise of --130dBc/Hz at 1MHz offset from 1. 13GHz carrier while only drawing an 8.0mA current from the 2.5V power supply.

Design of a 2.5GHz Low Phase-Noise LC-VCO in 0.35μm SiGe BiCMOS

This paper introduces a 2.5GHz low phase-noise cross-coupled LC-VCO realized in 0.35μm SiGe BiCMOS technology. The conventional definition of a VCO operating regime is revised from a new perspective. Analysis shows the importance of inductance and bias current selection for oscillator phase noise optimization. Differences between CMOS and BJT VCO design strategy are then analyzed and the conclusions are summarized. In this implementation, bonding wires form the resonator to improve the phase noise performance. The VCO is then integrated with other components to form a PLL frequency synthesizer with a loop bandwidth of 30kHz. Measurement shows a phase noise of - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from a 2.5GHz carrier. At a supply voltage of 3V, the VCO core consumes 8mA. To our knowledge,this is the first differential cross-coupled VCO in SiGe BiCMOS technology in China.

Implementation of a 6 GHz band TDD RF transceiver for the next generation mobile communication system

The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band and the channel bandwidth is up to 100 MHz. It operates in the time division duplex （TDD） mode and supports the multiple-input multipleoutput （MIMO） technique for the international mobile telecommunications （IMT）-advanced systems. The classical superheterodyne scheme is employed to achieve optimal performance. Design issues of the essential components such as low noise amplifier, power amplifier and local oscillators are described in detail. Measurement results show that the maximum linear output power of the RF transceiver is above 23 dBm, and the gain and noise figure of the low noise amplifier is around 24 dB and below 1 dB, respectively. Furthermore, the error vector magnitude （EVM） measurement shows that the performance of the developed RF transceiver is well beyond the requirements of the long term evolution （LTE）-advanced system. With up to 8 x 8 MIMO configuration, the RF transceiver supports more than a 1 Gbit/s data rate in field tests.

Low phase noise LC VCO design in CMOS technology

This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.

Frequency synthesizer for DRM/DAB/AM/FM RF front-end

This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.

A Novel Method to Compensate the Sigma-Delta Shaped Noise for Wide Band Fractional-N Frequency Synthesizers

A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.

A wideband low-phase-noise LC VCO for DRM/DAB frequency synthesizer

The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.

Noise Analysis of Analog Correlator

A noise model for the analog correlator used in the ultra wideband receivers is proposed due to lack of simulation capability on noise performance of the correlator in current EDA tools.The analog correlator circuit is divided into several parts to calculate the equivalent noise sources respectively.The ideal impulse generators,instead of the noise sources,are then applied to obtain the time varying transfer functions.Fourier transforms are carried out to explore the relationship between the noise input and output in frequency domain for each part.Then the symmetrical noise sources are grouped together and the periodicity of the circuit is utilized to further simplify the model.This model can be used to evaluate noise performance of the correlator.

Design of a 4.224GHz Quadrature LC-VCO

A 4. 224GHz quadrature voltage-controlled oscillator （QVCO） applied in MB-OFDM UWB synthesizers is implemented in 0.18μm RF-CMOS technology. An improved structure of the QVCO is presented for better phase noise. A novel configuration of a MOS varactor is designed for good linearity of K as well as a new digital capacitor controlled array topology with lower parasitic capacitance and lower Ron. Measurement results show a phase noise of - 90.4dBc/Hz at 100kHz offset and - 116.7dBc/Hz at 1MHz offset from a carrier close to 4. 224GHz. The power dissipation is 10. 55mW from a 1.8V supply.

Moments and Mean First—Passage Time of Parabolic—Bistable Potential System Driven by Colored Noise

A parabolic-bistable potential system driven by colored noise is studied. The exact analytical expressions of the stationary probability distribution (SPD) and the moments of the system are derived. Furthermore, the mean first-passage time is calculated by the use of two approximate methods, respectively. It is found that (i) the double peaks of SPD are rubbed-down into a flat single peak with the increasing of noise intensity; (ii) a minimum occurs on the curve of the second-order moment of the system vs. noise intensity at the point ; (iii) the results obtained by our approximate approach are in good agreement with the numerical calculations for either small or large correlation time , while the conventional steepest descent approximation leads to poor results.

A new three-phase 5-level current-source inverter

The new three-phase 5-level current-source inverter (CSI) proposed in this paper was developed by connecting three separate single-phase 5-level CSIs in series, and its operational principle was analyzed. There are two major problems existing in current-source multilevel inverters, one is the complex PWM control method (2-logic to 3-logic conversion), and the other is the problem of current-unbalance between different levels. A simple current-balance control method via DC current feedback is applied in each single-phase 5-level CSI cell to implement the current-balance control between different levels. And to reduce the output current harmonics, POD PWM control technique was used. Simulation and experimental results showed that this new three-phase 5-level CSI topology operates correctly.

BiScO_(3)-BiFeO_(3)-PbTiO_(3)-BaTiO_(3) high-temperature piezoelectric ceramic and its application on high-temperature acoustic emission sensor

Piezoelectric ceramic based high-temperature acoustic emission(AE)sensor is required urgently in the structural health monitoring of high-temperature fields.In this research,a series of 0.45(BiSc_(x)O_(3)-BiFe_(1-x)O_(3))-0.48PbTiO_(3)-0.07BaTiO_(3)(BSc_(x)Fe_(1-x)-PT-BT,n(Sc)/n(Fe)=0.4/0.6-0.6/0.4)ceramics with both high Curie temperature and large piezoelectric constant were presented.The structure and electrical properties of BSc_(x)Fe_(1-x)-PT-BT ceramics as a function of n(Sc)/n(Fe)have been systematically investigated.All the ceramics possess a perovskite structure,and the phase approaches from the rhombohedral toward the tetragonal phase with the decrease of n(Sc)/n(Fe).The BSc_(0.5)Fe_(0.5)-PT-BT and BSc_(0.5)Fe_(0.5)-PT-BT piezoelectric ceramics exhibit good piezoelectricity(d_(33)=250-281 pC/N),high Curie temperature(T_(C)=430-450℃)and excellent temperature stability.These improvements are greatly attributed to the balance between rhombohedral and tetragonal phase near morphotropic phase boundary with dense microstructure of ceramics.AE sensor based BSc_(0.5)Fe_(0.5)-PT-BT piezoelectric ceramic was designed,prepared and tested.The high-temperature stability of AE sensor was characterized through pencil-lead breaking with in situ high-temperature test.The noise of AE sensor is less than 40 dB,and the acoustic signal is up to 90 dB at 200℃.As a result,AE sensors based on BSc_(x)Fe_(1-x)-PT-BT piezoelectric ceramics are expected to be applied into the structural health monitoring of high temperature fields.