A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency de...A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.展开更多
文摘A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.
