Josephson传输线中流子振荡的相锁

具有cosφ损耗项的Josephson传输线中流子振荡的相锁动力学被详细地研究,找到了固定点的存在和稳定性的条件。

利用相锁值算法的脑电相同步测谎研究

相锁值(Phase Locking Value,PLV)是由相同步的概念下提出一种描述不同信号相关性(同步性)的算法,在脑电信号领域,其有效性已经得到了验证.本文针对当前测谎方法中脑电信号特征提取困难的问题,首次将相锁值的算法应用到脑电测谎领域中,研究谎言脑活动下不同脑区之间的相关性,通过相关性发现谎言的认知机制,并利用该相关性作为特征,使用支持向量机对说谎者和诚实者的两类信号进行模式识别,得到了88.50%的准确率,提出的方法验证了PLV在测谎应用中的有效性,为基于脑电信号的测谎提供了一种新的途径.

雅洁五金X系列锁头震撼亮相锁王争霸赛

2016年3月5日，广东省锁业协会借十周年庆典，诚邀全国锁业界朋友参与盛宴，并举办第二届全国锁王争霸赛。3000名通过国家报备的开锁达人报名参加，参赛人数创新高，本届参赛人数大于首届参赛人数的30倍，比赛规模盛大。

振幅耦合系统的混沌相同步

定义了动力系统间的复频率序参数,并用该量化指标研究了振幅耦合系统的混沌相同步。对系统作柱坐标变换,并使其振幅线性耦合,通过计算系统的平均频率、复频率序参数,研究了相同步和复频率序参数的对应关系。结果表明,随着耦合强度的增加,耦合系统的混沌相同步与复频率序参数之间有确定的对应关系,这说明复频率序参数作为衡量混沌相同步的一个量化指标是有效的。

一端受外力的多相位交联振荡器对的动态研究

对一端带有外力的多相位交联振荡器对的动态特性进行了研究，分析证明对频率在某个范围内的外力，该系统呈现出内部传输现象．本文还说明，当交联相位足够多时，对一端带外力的多相位交联振荡器对的研究可借助于其形式上的平均方程．

Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector

A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.

NEW CLOSED-LOOP DRIVING CIRCUIT OF SILICON MICROMACHINED VIBRATORY GYROSCOPE

A new closed-loop driving scheme for the silicon micromachined vibratory gyroscope (SMVG) is proposed. The push-pull driving is adopted and in-phase AC and reverse-phase DC voltages are applied in the driving electrodes placed in both sides of the active combs, respectively. Driving performance analyses show that the frequency spectrum between driving moments and noise signals is separated. Therefore, the model of the closed-loop control is set up with the phase lock loop (PLL). The requirements for phases and gains of the sinusoidal selfdrive-oscillation are met by PLL, thus the closed-loop circuit reaches the self-drive-oscillation. Phase conditions of the sinusoidal self-drive-oscillation and the characteristic of phase discrimination of the PLL are used to eliminate the coupling between driving and sense signals, and noise signals. Finally, experimental results show that the variations of both the driving frequency and the amplitude are all under 0.02%. The precision and the reliability of the gyroscope are greatly improved.

A Low Jitter PLL in a 90nm CMOS Digital Process

A low jitter phase-locked loop （PLL） that does not need analog resistors and capacitors is designed and fabrica- ted in a 90nm CMOS digital process. The metal parasitic capacitor is used in the PLL loop filter. Test results show that when the PLL is locked on 1. 989GHz, the RMS jitter is 3. 7977ps, the peak-to-peak jitter is 31. 225ps, and the power con- sumption is about 9mW. The locked output frequency range is from 125MHz to 2.7GHz.

Design and implementation of digital closed-loop drive control system of a MEMS gyroscope

In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.

2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS

The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.

2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.

2.5Gb/s Monolithic IC of Clock Recovery,Data Decision,and 1∶4 Demultiplexer

A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.

A NEW CONTROL METHOD FOR ULTRASONIC MOTOR

A new method for the control of the speed of an ultrasonic motor and its implementation are proposed. The method is merely used by detecting the time when motor′s monitor signal reaches a non zero reference value than a zero one, the direction, in which the driving frequency of the motor should be shifted, can be promptly calculated. With the aid of a CPU and the phase locked frequency doubling technique, the motor can be steadily driven in a wide range of frequency and the optimum frequency can be captured rapidly and precisely. Experiment shows that the above method is available.

A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation

A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.

Multipath mitigation method for tracking Galileo signals

In order to improve the performance of multipath mitigation in tracking Galileo signals, a new multipath mitigation method named early-late strobe correlator （ELSC） is proposed. By applying the strobe correlator used widely in global positioning system （GPS） scenarios to Galileo E1 signals, it can be found that the strobe correlator has an undesirable level of performance when the delay of multipath signals is about 0. 5 chip. Combining several strobe correlators, the ELSC can effectively mitigate the multipath effect especially for the multipath signals with the 0. 5 chip delay. The multipath error envelopes between the strobe correlator and the ELSC are compared for Galileo E1 signals. The simulation results indicate that the ELSC performs excellently on multipath mitigation, and can be applied in both Galileo scenarios and GPS scenarios.

A Novel Digital Transceiver for CT0 Standard

This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth-od. In the transmitter,a fractional-N phase locked loop （PLL） is utilized to realize the continuous phase frequency shift key （CPFSK） modulation,and a 2 Ts raised cosine （2RC） shaping technique is used to reduce the occupied bandwidth. In the receiver,a novel digital method is proposed to demodulate the 2RC CPFSK signal. This chip is fabricated using an SMIC 0.35μm mixed signal CMOS process with a die size of 2mm × 2mm. With an external low noise amplifier （LNA）,the sensitivity of the chip is better than -103dBm.

A 900MHz CMOS PLL/Frequency Synthesizer Initialization Circuit

A 900MHz CMOS PLL/frequency synthesizer using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented.The charge-pump current is insensitive to the changes of temperature and power supply.The value of the charge-pump current can be changed by switches,which are controlled by external signals.Thus the performance of the PLL,such as loop bandwidth,can be changed with the change of the charge-pump current.The loop filter initialization circuit can speed up the PLL when the power is on.A multi-modulus prescaler is used to fulfill the frequency synthesis.The circuit is designed using 0.18μm,1.8V,1P6M standard digital CMOS process.

A High Purity Integer-N Frequency Synthesizer in 0.35μm SiGe BiCMOS

An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized. All the building blocks are implemented with differential topology except for the off-chip loop filter. To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO. The frequency synthesizer operates from 2.39 to 2.72GHz with output power of about 0dBm. The measured closed-loop phase noise is - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from the carrier. The power level of the reference spur is less than - 72dBc. With a 3V power supply, the whole chip including the output buffers consumes 60mA.