A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works...A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.展开更多
In response to the downlink synchronization requirements of the user equipment(UE)or third-party radio equipment in fifth-generation(5G)mobile communication systems,a synchronization algorithm of primary synchroni-zat...In response to the downlink synchronization requirements of the user equipment(UE)or third-party radio equipment in fifth-generation(5G)mobile communication systems,a synchronization algorithm of primary synchroni-zation signal(PSS)was designed and developed in the 5G system based on block cross-correlation.According to the new characteristics of the 5G synchronization channel and broadcast channel,starting from the traditional downlink synchronization algorithm of long-term evolution(LTE),the detection performance of the algorithm under a low signal-to-noise ratio(SNR)is improved by introducing an incoherent accumulation,and the new scheme of joint coarse frequency offset estimation is used to improve the frequency offset estimation performance.Finally,the performance of the proposed synchronization algorithm is verified by conducting a simulation on a 5G downlink simulation platform based on MATLAB software.Simulation results show that the improved downlink synchronization algorithm has stable performance in the tapped delay line-C(TDL-C)and additive white Gaussian noise(AWGN)channels with large frequency deviation and low SNR.展开更多
According to the time&space conversion relations and different frequency phase detection principle,an ultra-high precision time&frequency measurement method is proposed in this paper.The higher accuracy and st...According to the time&space conversion relations and different frequency phase detection principle,an ultra-high precision time&frequency measurement method is proposed in this paper.The higher accuracy and stability of the speed of light and electromagnetic signals during the transmission in space or a specific medium enable the measurement of short time interval which uses the coincidence detection of signal’s transmission delay in length.The measurement precision better than 10 picoseconds can be easily obtained.The method develops the length vernier utilizing the stability of signal’s transmission delay,minimizes the fuzzy region of phase coincidence between the standard frequency signal and the measured signal,approaches the best phase coincidences and therefore improves the measurement precision which is higher than the precision provided by the traditional methods based on frequency processing.Besides,the method costs less than the traditional methods and can also solve the problem of the measurement of super-high frequency.Experimental results show the method can improve the measurement precision to 10 12/s in the time&frequency domain.展开更多
文摘A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.
基金The Social Development Projects of Jiangsu Science and Technology Department(No.BE2018704).
文摘In response to the downlink synchronization requirements of the user equipment(UE)or third-party radio equipment in fifth-generation(5G)mobile communication systems,a synchronization algorithm of primary synchroni-zation signal(PSS)was designed and developed in the 5G system based on block cross-correlation.According to the new characteristics of the 5G synchronization channel and broadcast channel,starting from the traditional downlink synchronization algorithm of long-term evolution(LTE),the detection performance of the algorithm under a low signal-to-noise ratio(SNR)is improved by introducing an incoherent accumulation,and the new scheme of joint coarse frequency offset estimation is used to improve the frequency offset estimation performance.Finally,the performance of the proposed synchronization algorithm is verified by conducting a simulation on a 5G downlink simulation platform based on MATLAB software.Simulation results show that the improved downlink synchronization algorithm has stable performance in the tapped delay line-C(TDL-C)and additive white Gaussian noise(AWGN)channels with large frequency deviation and low SNR.
基金supported by the National Natural Science Foundation of China (Grant No. U1304618)the Open Fund of Key Laboratory of Precision Navigation and Timing Technology of Chinese Academy of Sciences(Grant No. 2012PNTT01)+5 种基金the Postdoctoral Grant of China (Grant Nos. 2011M501446, 2012T50798)the Basic and Advanced Technology Research Foundation of Henan Province under Grant (Grant No. 122300410169)The Key Science and Technology Foundation of Henan Province under Grant (Grant No. 132102210180)the Doctor Fund of Zhengzhou University of Light Industry under (Grant No. 2011BSJJ031)the Scientific Research Fund of Zhengzhou University of Light Industry under (Grant No. 2012XJJ009)the Fundamental Research Funds for the Central Universities(Grant No. K5051204003)
文摘According to the time&space conversion relations and different frequency phase detection principle,an ultra-high precision time&frequency measurement method is proposed in this paper.The higher accuracy and stability of the speed of light and electromagnetic signals during the transmission in space or a specific medium enable the measurement of short time interval which uses the coincidence detection of signal’s transmission delay in length.The measurement precision better than 10 picoseconds can be easily obtained.The method develops the length vernier utilizing the stability of signal’s transmission delay,minimizes the fuzzy region of phase coincidence between the standard frequency signal and the measured signal,approaches the best phase coincidences and therefore improves the measurement precision which is higher than the precision provided by the traditional methods based on frequency processing.Besides,the method costs less than the traditional methods and can also solve the problem of the measurement of super-high frequency.Experimental results show the method can improve the measurement precision to 10 12/s in the time&frequency domain.
