Tapered Multimode Interference Combiners for Coherent Receivers

A new tapered multimode interference （MMl）-based coherent lightwave combiner is reported. A comprehensive theoretical analysis of mode behaviors in the tapered MMI waveguide is presented, and the output characteristics of the tapered MMI combiners with various structures are demonstrated. The combiner is fabricated on a silicon-on-insulator （SO1） substrate. Due to its advantages of having no end-facet reflection,easy extension to a multi-port configuration, high tolerance for fabrication errors, and compact size, the tapered MMI is a good candidate for a coherent lightwave combiner to be used in large-scale photonic integrated circuits.

Development of Novel Thin-Film SOI High Voltage MOSFET

Two kinds of thin-film SOI high voltage MOSFETs are developed.One is general structure,the other is novel two-drift-region structure.The gate width is 760μm,and the active area is 8.58×10 -2 mm 2.The experiments show that the breakdown voltages of the two-drift-region and general structures are 26V and 17V,respectively,and the on resistances are 65Ω and 80Ω,respectively.

SOICMOS Integrated Circuit of Laser Range Finding Working at High Temperatures

Modeling analysis of thin fully depleted SOICMOS technology has been done. Using ISETCAD software,the high temperature characteristics of an SOICMOS transistor were simulated in the temperature range of from 300 to 600K, and the whole circuit of a laser range finder was simulated with Verilog software. By wafer pro- cessing,a circuit of a laser range finder with complete function and parameters working at high temperatures has been developed. The simulated results agree with the test results. The test of the circuit function and parameters at normal and high temperature shows the realization of an SOICMOS integrated circuit with low power dissipation and high speed, which can be applied in laser range finding. By manufacturing this device, further study on high temperature characteristics of shorter channel SOICMOS integrated circuits can be conducted.

Fabrication and Evaluation of Bragg Gratings on Optimally Designed Silicon-on-Insulator Rib Waveguides Using Electron-Beam Lithography

The fabrication of Bragg gratings on silicon-on-insulator （SOI） rib waveguides using electron-beam lithography is presented. The grating waveguide is optimally designed for actual photonic integration. Experimental and theoretical evaluations of the Bragg grating are demonstrated. By thinning the SOl device layer and deeply etching the Bragg grating, a large grating coupling coefficient of 30cm^-1 is obtained.

Silicon-on-insulator 1×2 Y-junction Optical Switch Based on Waveguide-vanishing Effect^①②

The silicon-on-insulator(SOI)1×2Y-junction optical waveguide switch has been proposed and fabricated,which is based on the large cross-section single-mode rib waveguide condition,the waveguide-vanishing effect and the free-carrier plasma dispersion effect.In the switch,the SOI technique utilizer silicon and silicon dioxide thermal bonding and back-polishing.The insertion loss and extinction ratio of the device are measured to be less than 4.78dB and 20.8dB respectively at a wavelength of 1.3μm and an injection current of 45mA.Response time is about 160ns.

Simulation of a Double-Gate Dynamic Threshold Voltage Fully Depleted Silicon-on-Insulator nMOSFET

A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.

Off-State Breakdown Characteristics of PDSOI nMOSFETs

Partially-depleted silicon-on-insulator（PDSOI）floating-body（FB）nMOSFETs and H-gate type body-contacted（BC）nMOSFETs are fabricated with different back channel implantation dosages. The off-state breakdown characteristics of these devices are presented. The off-state breakdown voltages of the FB nMOSFETs increase from 5.2 to 6. 7V, and those of the H-gate type BC nMOSFETs decrease from 11.9 to 9V as the back channel implantation dosages increase from 1.0 ×10^13 to 1.3×10^13 cm^-2. By measuring the parasitic bipolar transistor static gain and the breakdown characteristics of the pn junction between the drain and the body, the differences between the breakdown mechanisms of the FB and H-gate type BC nMOSFETs are analyzed and explained qualitatively.

Thin-Film Accumulation-Mode SOI pMOSFET

Thin-film accumulation-mode SOI pMOSFETs are fabricated and investigated.Their characteristics are compared with those of thin-film inversion-mode pMOSFETs.The subthreshold slope is 69mV/decade,and it almost has no DIBL effect.The breakdown voltage is 10.5V,which is increased by 40% relative to thin-film inversion-mode pMOSFET.The saturation current is 130μA/μm,which is enhanced by 27% compared with inversion-mode pMOSFET.The per-stage propagation delay of 101-stage SOI CMOS ring oscillator is 56ps with 3V supply voltage.

Novel lateral insulated gate bipolar transistor on SOI substrate for optimizing hot-carrier degradation

A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.

Analysis and Simulation of S-shaped Waveguide in Silicon-on-insulator

The simulation and analysis of S-shaped waveguide bend are presented.Bend radius larger than 30 mm assures less than 0.5 dB radiation loss for a 4-μm-wide silicon-on-insulator waveguide bend with 2-μm etch depth.Intersection angle greater than 20° provides negligible crosstalk (<-30 dB) and very low insertion loss.Any reduction in bend radius and intersection angle is at the cost of the degradation of characteristics of bent waveguide and intersecting waveguide, respectively.

Photoelastic Fabry－Perot Optical Modulator Based on a Silicon－on－Insulator Structure

A simple photoelastic optical modulator with a Fabry-Perot cavity based on the silicon-on-insulator system was fabricated. A 50 % modulation depth has been obtained at current density of about 1. 5 x 103 A/cm2. The insertion loss was about 15 dB.

New Level-Shift LDMOS Structure for a 600 V-HVIC on Thick SOl

A novel level-shift LDMOS （lateral double-diffused metal oxide semiconductor） structure with the HV （high voltage） -interconnection for a 600 V-HVIC （high voltage integrated circuit） on thick SOI （silicon on insulator） is proposed. There are two original points in the proposed structure. One is the formation of the double floating p-layers under the HV-interconnection to prevent potential distribution in the drift from disturbing due to the HV-interconnection, and the other is a good combination between the LDMOS structure and multiple trench isolation to obtain the isolation performance over 600 V. From the proposed structure, the high blocking capability of the LDMOS, including both off- and on-breakdown voltages over 600 V and high hot carrier instability, and the isolation performance over 1,200 V can be obtained successfully. This paper will show numerical and experimental results in detail.

Back-Gate Effect of SOI LDMOSFETs

0.5μm-gate-length lateral double-diffused metal-oxide-semiconductor field-effect transistors （LDMOSFETs） with low barrier body contact （LBBC） and body tied to the source （BTS） were fabricated on silicon-on-insulator （SOI） substrates. The back-gate effects on front-channel subthreshold characteristics, on-resistance, and off-state breakdown characteristics of these devices are studied in detail. The LDMOSFETs with the LBBC structure show less back-gate effect than those with the BTS structure due to better control of the floating body effect and suppression of the parasitic backchannel leakage current. A model for the SOl LDMOSFETs has been given,including the front- and back-channel conductions as well as the bias-dependent series resistance.

A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node

This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.

Subwavelength grating devices in silicon photonics

Subwavelength grating(SWG) waveguides in silicon-on-insulator are emerging as an enabling technology for implementing compact, high-performance photonic integrated devices and circuits for signal processing and sensing applications. We provide an overview of our recent work on developing wavelength selective SWG waveguide filters based on Bragg gratings and ring resonators, as well as optical delay lines. These components increase the SWG waveguide component toolbox and can be used to realize more complex photonic integrated circuits with enhanced or new functionality.

Non-blocking four-port optical router based on thermooptic silicon microrings

By using silicon-on-insulator(SOI) platform, 12 channel waveguides, and four parallel-coupling one-microring resonator routing elements, a non-blocking four-port optical router is proposed. Structure design and optimization are performed on the routing elements at 1 550 nm. At drop state with a power consumption of 0 m W, the insertion loss of the drop port is less than 1.12 d B, and the crosstalk between the two output ports is less than-28 d B; at through state with a power consumption of 22 m W, the insertion loss of the through port is less than 0.45 d B, and the crosstalk between the two output ports is below-21 d B. Routing topology and function are demonstrated for the four-port optical router. The router can work at nine non-blocking routing states using the thermo-optic(TO) effect of silicon for tuning the resonance of each switching element. Detailed characterizations are presented, including output spectrum, insertion loss, and crosstalk. According to the analysis on all the data links of the router, the insertion loss is within the range of 0.13—3.36 d B, and the crosstalk is less than-19.46 d B. The router can meet the need of large-scale optical network-on-chip(ONo C).

A fast SOI-based variable optical attenuator with a p-i-n structure with low polarization dependent loss

According to the plasma dispersion effect of silicon(Si),a silicon-on-insulator(SOI) based variable optical attenuator(VOA) with p-i-n lateral diode structure is demonstrated in this paper.A wire rib waveguide with sub-micrometer cross section is adopted.The device is only about 2 mm long.The power consumption of the VOA is 76.3 mW(0.67 V,113.9 mA),and due to the carrier absorption,the polarization dependent loss(PDL) is 0.1dB at 20dB attenuation.The raise time of the VOA is 34.5 ns,the fall time is 37 ns,and the response time is 71.5 ns.

Rabi oscillation generation in the microring resonator system with double-series ring resonators

In this paper, a microring resonator(MRR) system using double-series ring resonators is proposed to generate and investigate the Rabi oscillations. The system is made up of silicon-on-insulator and attached to bus waveguide which is used as propagation and oscillation medium. The scattering matrix method is employed to determine the output signal intensity which acts as the input source between two-level Rabi oscillation states, where the increase of Rabi oscillation frequency with time is obtained at the resonant state. The population probability of the excited state is higher and unstable at the optical resonant state due to the nonlinear spontaneous emission process. The enhanced spontaneous emission can be managed by the atom(photon) excitation, which can be useful for atomic related sensors and single-photon source applications.