A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabric...A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabrication processes are fully compatible with conventional CMOS process,including salicide technology.The CMOS device,inverter,and CMOS ring oscillator of this structure with normal poly silicon and W/TiN gate electrode are fabricated respectively.Driving current and sub threshold characteristics of CMOS FinFET on Si substrate with actual gate length of 110nm are studied.The inverter operates correctly and minimum per stage delay of 201 stage ring oscillator is 146ps at V d=3V.The result indicates the device is a promising candidate for the application of future VLSI circuit.展开更多
Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular be...Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.展开更多
A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by...A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.展开更多
The silicon nano-crystalline (nc-Si) film is fabricated on <100> orientation,0.01Ω·cm resistivity,and p-type boron-doped silicon wafer by the anodic etching.The microstructure and the orientation of nc-Si ...The silicon nano-crystalline (nc-Si) film is fabricated on <100> orientation,0.01Ω·cm resistivity,and p-type boron-doped silicon wafer by the anodic etching.The microstructure and the orientation of nc-Si are examined by the scanning electron microscopy,transmission electron microscopy,and X-ray diffraction spectroscopy,respectively.The average size of particle is estimated by Raman spectroscopy.The results show that the particle size of nc-Si film is scattered from 10nm to 20nm,the alignment is compact,the orientation is uniform,the expansion of lattice constant is negligible,and mechanical robustness and stability are good.The correlations between film structure and the experiment parameters such as etching time,HF concentration,and etching current density are discussed.As a potential application,efficient field emission is observed from the nc-Si film,and the turn-on field is about 3V/μm at 0.1μA/cm 2 of current density,which is close to carbon nanotube film's.展开更多
A new 2D analytical model for the surface electrical field distribution and optimization of bulk-silicon double RESURF devices is presented. Based on the solution to the 2D Poisson＇s equation, the model gives the inf...A new 2D analytical model for the surface electrical field distribution and optimization of bulk-silicon double RESURF devices is presented. Based on the solution to the 2D Poisson＇s equation, the model gives the influence on the surface electrical field of the drain bias and structure parameters such as the doping concentration,the depth and the position of the p-top region, the thickness and the doping concentration of the drift region, and the substrate doping concentration. The dependence of breakdown voltage on the length and doping concentration of the drift region is also calculated. Further more,an effective way to gain the optimum high-voltage is also proposed. All analytical results are verified by simulation results obtained by MEDICI and previous experimental data,showing the validity of the model presented here.展开更多
Two kinds of thin-film SOI high voltage MOSFETs are developed.One is general structure,the other is novel two-drift-region structure.The gate width is 760μm,and the active area is 8.58×10 -2 mm 2.The experim...Two kinds of thin-film SOI high voltage MOSFETs are developed.One is general structure,the other is novel two-drift-region structure.The gate width is 760μm,and the active area is 8.58×10 -2 mm 2.The experiments show that the breakdown voltages of the two-drift-region and general structures are 26V and 17V,respectively,and the on resistances are 65Ω and 80Ω,respectively.展开更多
Through the theoretical analysis and computer simulation,the optimized design principles for Si/SiGe PMOSFETs are given,including the choice of gate materials,the determination of Ge percentage and the profile in SiGe...Through the theoretical analysis and computer simulation,the optimized design principles for Si/SiGe PMOSFETs are given,including the choice of gate materials,the determination of Ge percentage and the profile in SiGe channel,the thickness optimization of dioxide and silicon cap layer,and the adjustment of threshold voltage.In light of them,a SiGe PMOSFET is designed and fabricated successfully.The measurements indicate that the transconductance is 45mS/mm (300K) and 92mS/mm (77K) for SiGe PMOSFET's (L=2μm),while it is 33mS/mm (300K) and 39mS/mm (77K) for Si PMOSFET.展开更多
The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method dir...The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.展开更多
In a previous study, structure of silica gels prepared in a high magnetic field was investigated. While a direct application of such anisotropic silica gels is for an optical anisotropic medium possessing chemical res...In a previous study, structure of silica gels prepared in a high magnetic field was investigated. While a direct application of such anisotropic silica gels is for an optical anisotropic medium possessing chemical resistance, we show here their possibility of medium in materials processing. In this direction, for example, silica hydrogels have so far been used as media of crystal growth. In this paper, as opposed to the soft-wet state, dried silica gels have been investigated. We have found that lead （II） nanocrystallites were formed induced by electron irradiation to lead （ll）-doped dried Hydrogels made from a sodium metasilicate solution doped with silica gels prepared in a high magnetic field such as B = 10 T. lead （II） acetate were prepared. The dried specimens were irradiated by electrons in a transmission electron microscope environment. Electron diffraction patterns indicated the crystallinity of lead （II） nanocrystallites depending on B. An advantage of this processing technique is that the crystallinity can be controlled through the strength of magnetic field B applied during gel preparation. Specific skills are not required to control the strength of magnetic field.展开更多
Combining sintering additive with field assisted sintering,stereolithographical dense Si3N4 ceramics was successfully fabricated.Owing to a large amount of polymer during the stereolithography,the green parts have the...Combining sintering additive with field assisted sintering,stereolithographical dense Si3N4 ceramics was successfully fabricated.Owing to a large amount of polymer during the stereolithography,the green parts have the characteristics of low powder loading and high porosity.Adjusting the process parameters such as sintering temperature and soaking time can effectively improve the density of the specimens.The stress exponent n of all specimens is in a range of 1 and 2,which is derived from a modified sintering kinetics model.The apparent activation energy Qd of stereolithographic Si_(3)N_(4) ceramics sintered with applied pressures of 30 MPa,40 MPa,and 50 MPa is 384.75,276.61 and 193.95 kJ/mol,respectively,suggesting that the densification dynamic process is strengthened by raising applied pressure.The grain boundary slipping plays a dominating role in the densification of stereolithographic Si3N4 ceramics.The Vickers hardness and fracture toughness of stereolithographic Si3N4 ceramics are HV10/10(1347.9±2.4)and(6.57±0.07)MPaAbstract:Combining sintering additive with field assisted sintering,stereolithographical dense Si3N4 ceramics was successfully fabricated.Owing to a large amount of polymer during the stereolithography,the green parts have the characteristics of low powder loading and high porosity.Adjusting the process parameters such as sintering temperature and soaking time can effectively improve the density of the specimens.The stress exponent n of all specimens is in a range of 1 and 2,which is derived from a modified sintering kinetics model.The apparent activation energy Qd of stereolithographic Si3N4 ceramics sintered with applied pressures of 30 MPa,40 MPa,and 50 MPa is 384.75,276.61 and 193.95 kJ/mol,respectively,suggesting that the densification dynamic process is strengthened by raising applied pressure.The grain boundary slipping plays a dominating role in the densification of stereolithographic Si3N4 ceramics.The Vickers hardness and fracture toughness of stereolithographic Si3N4 ceramics are HV10/10(1347.9±2.4)and(6.57±0.07)MPa·m^(1/2),respectively.展开更多
A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET.Experimental results were used to validate this model.Th...A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET.Experimental results were used to validate this model.The extracted parameters from our model were tOX=20 nm,ND=1×1016cm 3,tSSi=13.2 nm,consistent with the experimental values.The results show that the simulation results agree with experimental data well.It is found that the plateau can be strongly affected by doping concentration,strained-Si layer thickness and mass fraction of Ge in the SiGe layer.The model has been implemented in the software for strained silicon MOSFET parameter extraction,and has great value in the design of the strained-Si/SiGe devices.展开更多
文摘A CMOS FinFET fabricated on bulk silicon substrate is demonstrated.Besides owning a FinFET structure similar to the original FinFET on SOI,the device combines a grooved planar MOSFET in the Si substrate and the fabrication processes are fully compatible with conventional CMOS process,including salicide technology.The CMOS device,inverter,and CMOS ring oscillator of this structure with normal poly silicon and W/TiN gate electrode are fabricated respectively.Driving current and sub threshold characteristics of CMOS FinFET on Si substrate with actual gate length of 110nm are studied.The inverter operates correctly and minimum per stage delay of 201 stage ring oscillator is 146ps at V d=3V.The result indicates the device is a promising candidate for the application of future VLSI circuit.
文摘Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.
文摘A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.
文摘The silicon nano-crystalline (nc-Si) film is fabricated on <100> orientation,0.01Ω·cm resistivity,and p-type boron-doped silicon wafer by the anodic etching.The microstructure and the orientation of nc-Si are examined by the scanning electron microscopy,transmission electron microscopy,and X-ray diffraction spectroscopy,respectively.The average size of particle is estimated by Raman spectroscopy.The results show that the particle size of nc-Si film is scattered from 10nm to 20nm,the alignment is compact,the orientation is uniform,the expansion of lattice constant is negligible,and mechanical robustness and stability are good.The correlations between film structure and the experiment parameters such as etching time,HF concentration,and etching current density are discussed.As a potential application,efficient field emission is observed from the nc-Si film,and the turn-on field is about 3V/μm at 0.1μA/cm 2 of current density,which is close to carbon nanotube film's.
文摘A new 2D analytical model for the surface electrical field distribution and optimization of bulk-silicon double RESURF devices is presented. Based on the solution to the 2D Poisson＇s equation, the model gives the influence on the surface electrical field of the drain bias and structure parameters such as the doping concentration,the depth and the position of the p-top region, the thickness and the doping concentration of the drift region, and the substrate doping concentration. The dependence of breakdown voltage on the length and doping concentration of the drift region is also calculated. Further more,an effective way to gain the optimum high-voltage is also proposed. All analytical results are verified by simulation results obtained by MEDICI and previous experimental data,showing the validity of the model presented here.
文摘Two kinds of thin-film SOI high voltage MOSFETs are developed.One is general structure,the other is novel two-drift-region structure.The gate width is 760μm,and the active area is 8.58×10 -2 mm 2.The experiments show that the breakdown voltages of the two-drift-region and general structures are 26V and 17V,respectively,and the on resistances are 65Ω and 80Ω,respectively.
文摘Through the theoretical analysis and computer simulation,the optimized design principles for Si/SiGe PMOSFETs are given,including the choice of gate materials,the determination of Ge percentage and the profile in SiGe channel,the thickness optimization of dioxide and silicon cap layer,and the adjustment of threshold voltage.In light of them,a SiGe PMOSFET is designed and fabricated successfully.The measurements indicate that the transconductance is 45mS/mm (300K) and 92mS/mm (77K) for SiGe PMOSFET's (L=2μm),while it is 33mS/mm (300K) and 39mS/mm (77K) for Si PMOSFET.
基金special funds of major state basic research projects (G20000365)
文摘The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.
文摘In a previous study, structure of silica gels prepared in a high magnetic field was investigated. While a direct application of such anisotropic silica gels is for an optical anisotropic medium possessing chemical resistance, we show here their possibility of medium in materials processing. In this direction, for example, silica hydrogels have so far been used as media of crystal growth. In this paper, as opposed to the soft-wet state, dried silica gels have been investigated. We have found that lead （II） nanocrystallites were formed induced by electron irradiation to lead （ll）-doped dried Hydrogels made from a sodium metasilicate solution doped with silica gels prepared in a high magnetic field such as B = 10 T. lead （II） acetate were prepared. The dried specimens were irradiated by electrons in a transmission electron microscope environment. Electron diffraction patterns indicated the crystallinity of lead （II） nanocrystallites depending on B. An advantage of this processing technique is that the crystallinity can be controlled through the strength of magnetic field B applied during gel preparation. Specific skills are not required to control the strength of magnetic field.
基金Project(20170410221235842)supported by Shenzhen Technical Innovation and Tackling Program,ChinaProject(2019zzts859)supported by the Fundamental Research Funds for the Central Universities,ChinaProject(20203BBE53053)supported by Key R&D Project of Jiangxi Provincial Department of Science and Technology,China。
文摘Combining sintering additive with field assisted sintering,stereolithographical dense Si3N4 ceramics was successfully fabricated.Owing to a large amount of polymer during the stereolithography,the green parts have the characteristics of low powder loading and high porosity.Adjusting the process parameters such as sintering temperature and soaking time can effectively improve the density of the specimens.The stress exponent n of all specimens is in a range of 1 and 2,which is derived from a modified sintering kinetics model.The apparent activation energy Qd of stereolithographic Si_(3)N_(4) ceramics sintered with applied pressures of 30 MPa,40 MPa,and 50 MPa is 384.75,276.61 and 193.95 kJ/mol,respectively,suggesting that the densification dynamic process is strengthened by raising applied pressure.The grain boundary slipping plays a dominating role in the densification of stereolithographic Si3N4 ceramics.The Vickers hardness and fracture toughness of stereolithographic Si3N4 ceramics are HV10/10(1347.9±2.4)and(6.57±0.07)MPaAbstract:Combining sintering additive with field assisted sintering,stereolithographical dense Si3N4 ceramics was successfully fabricated.Owing to a large amount of polymer during the stereolithography,the green parts have the characteristics of low powder loading and high porosity.Adjusting the process parameters such as sintering temperature and soaking time can effectively improve the density of the specimens.The stress exponent n of all specimens is in a range of 1 and 2,which is derived from a modified sintering kinetics model.The apparent activation energy Qd of stereolithographic Si3N4 ceramics sintered with applied pressures of 30 MPa,40 MPa,and 50 MPa is 384.75,276.61 and 193.95 kJ/mol,respectively,suggesting that the densification dynamic process is strengthened by raising applied pressure.The grain boundary slipping plays a dominating role in the densification of stereolithographic Si3N4 ceramics.The Vickers hardness and fracture toughness of stereolithographic Si3N4 ceramics are HV10/10(1347.9±2.4)and(6.57±0.07)MPa·m^(1/2),respectively.
基金Projects(51308040203,6139801)supported by National Ministries and Commissions,ChinaProjects(72105499,72104089)supported by the Fundamental Research Funds for the Central Universities,ChinaProject(2010JQ8008)supported by the Natural Science Basic Research Plan in Shaanxi Province of China
文摘A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET.Experimental results were used to validate this model.The extracted parameters from our model were tOX=20 nm,ND=1×1016cm 3,tSSi=13.2 nm,consistent with the experimental values.The results show that the simulation results agree with experimental data well.It is found that the plateau can be strongly affected by doping concentration,strained-Si layer thickness and mass fraction of Ge in the SiGe layer.The model has been implemented in the software for strained silicon MOSFET parameter extraction,and has great value in the design of the strained-Si/SiGe devices.
