A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmis...A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmission line pulse(TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current(It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 m A/μm2 to 1.884 m A/μm2. Moreover, due to their different turn-on resistances(Ron), the device with smaller channel length(L) owns a stronger ESD robustness per unit area.展开更多
A new low leakage 3×VDD-tolerant electrostatic discharge(ESD)detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process.Stacked-transistors technique is...A new low leakage 3×VDD-tolerant electrostatic discharge(ESD)detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process.Stacked-transistors technique is adopted to sustain high-voltage stress and reduce leakage current.No NMOSFET operates in high voltage range and it is unnecessary to use any deep N-well.The proposed detection circuit can generate a 38 mA current to turn on the substrate triggered silicon-controlled rectifier(STSCR)under the ESD stress.Under normal operating conditions,all the devices are free from over-stress voltage threat.The leakage current is 88 nA under 3×VDD bias at 25°C.The simulation result shows the circuit can be successfully used for 3×VDD-tolerant I/O buffer.展开更多
基金Project(NCET-11-0975)supported by Program for New Century Excellent Talents in University of Ministry of Education of ChinaProjects(61233010,61274043)supported by the National Natural Science Foundation of China
文摘A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmission line pulse(TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current(It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 m A/μm2 to 1.884 m A/μm2. Moreover, due to their different turn-on resistances(Ron), the device with smaller channel length(L) owns a stronger ESD robustness per unit area.
基金supported by the National Natural Science Foundation of China (Grant Nos. 61076097,60936005)in part by Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China Program (Grant No. 20110203110012)
文摘A new low leakage 3×VDD-tolerant electrostatic discharge(ESD)detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process.Stacked-transistors technique is adopted to sustain high-voltage stress and reduce leakage current.No NMOSFET operates in high voltage range and it is unnecessary to use any deep N-well.The proposed detection circuit can generate a 38 mA current to turn on the substrate triggered silicon-controlled rectifier(STSCR)under the ESD stress.Under normal operating conditions,all the devices are free from over-stress voltage threat.The leakage current is 88 nA under 3×VDD bias at 25°C.The simulation result shows the circuit can be successfully used for 3×VDD-tolerant I/O buffer.
