在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以...在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 。展开更多
A novel low temperature poly\|Si(LTPS) ultra\|thin channel thin film transistor (UTC\|TFT) technology is proposed. The UTC\|TFT has an ultra\|thin channel region (30nm) and a thick drain/source region (300nm). The ult...A novel low temperature poly\|Si(LTPS) ultra\|thin channel thin film transistor (UTC\|TFT) technology is proposed. The UTC\|TFT has an ultra\|thin channel region (30nm) and a thick drain/source region (300nm). The ultra\|thin channel region that can result in a lower grain\|boundary trap density in the channel is connected to the heavily\|doped thick drain/source region through a lightly\|doped overlapped region. The overlapped lightly\|doped region provides an effective way for the electric field to spread in the channel near the drain at high drain biases, thereby reducing the electric field there significantly. Simulation results show the UTC\|TFT experiences a 50% reduction in peak lateral electric field compared to that of the conventional TFT. With the low grain\|boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are achieved in the UTC\|TFT. Moreover, this technology provides the complementary LTPS\|TFTs with more than 2 times increase in on\|current, 3.5 times reduction in off\|current compared to the conventional thick channel LTPS TFTs.展开更多
Partially-depleted silicon-on-insulator（PDSOI）floating-body（FB）nMOSFETs and H-gate type body-contacted（BC）nMOSFETs are fabricated with different back channel implantation dosages. The off-state breakdown charact...Partially-depleted silicon-on-insulator（PDSOI）floating-body（FB）nMOSFETs and H-gate type body-contacted（BC）nMOSFETs are fabricated with different back channel implantation dosages. The off-state breakdown characteristics of these devices are presented. The off-state breakdown voltages of the FB nMOSFETs increase from 5.2 to 6. 7V, and those of the H-gate type BC nMOSFETs decrease from 11.9 to 9V as the back channel implantation dosages increase from 1.0 ×10^13 to 1.3×10^13 cm^-2. By measuring the parasitic bipolar transistor static gain and the breakdown characteristics of the pn junction between the drain and the body, the differences between the breakdown mechanisms of the FB and H-gate type BC nMOSFETs are analyzed and explained qualitatively.展开更多
GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold v...GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold voltage rolling off and DIBL effect is thoroughly investigated,as well as the influence of the Ge concentration and silicon film thickness.The Ge concentration should be carefully chosen as a tradeoff between the driving current and SCE improvement.The detailed physics is explained.展开更多
The process parameters are adjusted and the process procedure is simplified on the basis of precursor's work and the strained Si channel SiGe n MOSFET is fabricated successfully.This n MOSFET takes the strained...The process parameters are adjusted and the process procedure is simplified on the basis of precursor's work and the strained Si channel SiGe n MOSFET is fabricated successfully.This n MOSFET takes the strained Si layer(which is deposited on the relaxed SiGe buffer layer) as current channel and can provide a 48 5% improvement in electron mobility while keeping the gate voltage as 1V.展开更多
Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) using P+ (phosphor ion) implantation technology is successfully fabricated. P+ implantation into SiGe virtual substrate induces a narrow de...Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) using P+ (phosphor ion) implantation technology is successfully fabricated. P+ implantation into SiGe virtual substrate induces a narrow defect region slightly below the SiGe/Si interface,which gives rise to strongly enhanced strain relaxation of SiGe virtual substrate. X-Ray Diffraction (XRD) tests show that the degree of relaxation of SiGe layer is 96% while 85% before implantation. After annealed,the sample appeared free of Threading Dislocation densities (TDs) within the SiGe layer to the limit of Trans-mission Electron Microscopy (TEM) analysis. Atomic Force Microscope (AFM) test of strained Si channel surface shows that Root Mean Square (RMS) is 1.1nm. The Direct Current (DC) characters measured by HP 4155B indicate that the maximum saturated transconductance is twice bigger than that of bulk Si PMOSFET.展开更多
Biaxial strain technology is a promising way to improve the mobility of both electrons and holes, while （100） channel direction appears as to be an effective booster of hole mobility in particular. In this work, the...Biaxial strain technology is a promising way to improve the mobility of both electrons and holes, while （100） channel direction appears as to be an effective booster of hole mobility in particular. In this work, the impact of biaxial strain together with （100） channel orientation on hole mobility is explored. The biaxial strain was incorporated by the growth of a relaxed SiGe buffer layer,serving as the template for depositing a Si layer in a state of biaxial tensile strain. The channel orientation was implemented with a 45^o rotated design in the device layout,which changed the channel direction from （110） to （100） on Si （001） surface. The maximum hole mobility is enhanced by 30% due to the change of channel direction from （110） to （100） on the same strained Si （s-Si） p-MOSFETs,in addition to the mobility enhancement of 130% when comparing s-Si pMOS to bulk Si pMOS both along （110） channels. Discussion and analysis are presented about the origin of the mobility enhancement by channel orientation along with biaxial strain in this work.展开更多
文摘在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 。
文摘A novel low temperature poly\|Si(LTPS) ultra\|thin channel thin film transistor (UTC\|TFT) technology is proposed. The UTC\|TFT has an ultra\|thin channel region (30nm) and a thick drain/source region (300nm). The ultra\|thin channel region that can result in a lower grain\|boundary trap density in the channel is connected to the heavily\|doped thick drain/source region through a lightly\|doped overlapped region. The overlapped lightly\|doped region provides an effective way for the electric field to spread in the channel near the drain at high drain biases, thereby reducing the electric field there significantly. Simulation results show the UTC\|TFT experiences a 50% reduction in peak lateral electric field compared to that of the conventional TFT. With the low grain\|boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are achieved in the UTC\|TFT. Moreover, this technology provides the complementary LTPS\|TFTs with more than 2 times increase in on\|current, 3.5 times reduction in off\|current compared to the conventional thick channel LTPS TFTs.
文摘Partially-depleted silicon-on-insulator（PDSOI）floating-body（FB）nMOSFETs and H-gate type body-contacted（BC）nMOSFETs are fabricated with different back channel implantation dosages. The off-state breakdown characteristics of these devices are presented. The off-state breakdown voltages of the FB nMOSFETs increase from 5.2 to 6. 7V, and those of the H-gate type BC nMOSFETs decrease from 11.9 to 9V as the back channel implantation dosages increase from 1.0 ×10^13 to 1.3×10^13 cm^-2. By measuring the parasitic bipolar transistor static gain and the breakdown characteristics of the pn junction between the drain and the body, the differences between the breakdown mechanisms of the FB and H-gate type BC nMOSFETs are analyzed and explained qualitatively.
文摘GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold voltage rolling off and DIBL effect is thoroughly investigated,as well as the influence of the Ge concentration and silicon film thickness.The Ge concentration should be carefully chosen as a tradeoff between the driving current and SCE improvement.The detailed physics is explained.
文摘The process parameters are adjusted and the process procedure is simplified on the basis of precursor's work and the strained Si channel SiGe n MOSFET is fabricated successfully.This n MOSFET takes the strained Si layer(which is deposited on the relaxed SiGe buffer layer) as current channel and can provide a 48 5% improvement in electron mobility while keeping the gate voltage as 1V.
基金Supported by the Funds of National Key Laboratory of Analog IC (2000JS09.3.1.DZ02).
文摘Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) using P+ (phosphor ion) implantation technology is successfully fabricated. P+ implantation into SiGe virtual substrate induces a narrow defect region slightly below the SiGe/Si interface,which gives rise to strongly enhanced strain relaxation of SiGe virtual substrate. X-Ray Diffraction (XRD) tests show that the degree of relaxation of SiGe layer is 96% while 85% before implantation. After annealed,the sample appeared free of Threading Dislocation densities (TDs) within the SiGe layer to the limit of Trans-mission Electron Microscopy (TEM) analysis. Atomic Force Microscope (AFM) test of strained Si channel surface shows that Root Mean Square (RMS) is 1.1nm. The Direct Current (DC) characters measured by HP 4155B indicate that the maximum saturated transconductance is twice bigger than that of bulk Si PMOSFET.
文摘Biaxial strain technology is a promising way to improve the mobility of both electrons and holes, while （100） channel direction appears as to be an effective booster of hole mobility in particular. In this work, the impact of biaxial strain together with （100） channel orientation on hole mobility is explored. The biaxial strain was incorporated by the growth of a relaxed SiGe buffer layer,serving as the template for depositing a Si layer in a state of biaxial tensile strain. The channel orientation was implemented with a 45^o rotated design in the device layout,which changed the channel direction from （110） to （100） on Si （001） surface. The maximum hole mobility is enhanced by 30% due to the change of channel direction from （110） to （100） on the same strained Si （s-Si） p-MOSFETs,in addition to the mobility enhancement of 130% when comparing s-Si pMOS to bulk Si pMOS both along （110） channels. Discussion and analysis are presented about the origin of the mobility enhancement by channel orientation along with biaxial strain in this work.
