This paper discusses the design of a 10 Gb/s laser diode driver implemented in SiGe BiCMOS technology. The laser diode driver is composed of an input buffer, a predriver circuit and an output current switch stage. Wit...This paper discusses the design of a 10 Gb/s laser diode driver implemented in SiGe BiCMOS technology. The laser diode driver is composed of an input buffer, a predriver circuit and an output current switch stage. With the current mode logic （CML） structure, the input buffer and the predriver circuit have the capability of transmission and amplification of high speed data. By employing MOS-HBT cascode structure as the output stage, the laser diode driver exhibits very high speed and efficiency working at the 10 Gb/s data rate. The core circuit is operated under a 3. 3 V supply, while the output stage is operated under 5.5 V for sufficient headroom across the laser diode. The chip occupies a die area of 600 μm × 800μm. Measurements on chip show clear electrical eye diagrams over 10 Gb/s, which can well meet the specifications defined by SDH STM64/SONET OC192 and a 10 Gb/s Ethemet eye mask. Under a 5. 5 V supply voltage, the maximum output swing is 3.0 V with a 50 12 load （the corresponding modulation current is 60 mA）, and the total power dissipation is 660 mW.展开更多
A low power 640×480 OLED-on-silicon chip design that used in microdisplay was presented. A novel pixel circuit was proposed to meet the special requirement of OLED-on-silicon. The novel pixel consists of three tr...A low power 640×480 OLED-on-silicon chip design that used in microdisplay was presented. A novel pixel circuit was proposed to meet the special requirement of OLED-on-silicon. The novel pixel consists of three transistors and one capacitor （3T 1C）. It has simple structure and can effectively reduce the current glitch generated during the AC driving from 55 pA to 7.5 pA, so that it can improve the precision of grayscale of display as well as extend the lifetime of （]）LED material. Except for the pixel array, low power row driver, column driver and other functional modules were also integrated on the chip. Several techniques were adopted to reduce the power consumption and frequency requirement of the chip. Finally, a 16×3×12 resolution chip was fabricated with standard 0.35 μm CMOS process of CSM and the chip can operate correctly.展开更多
This paper presents the fabrication of squama-shape micro/nano multi-scale structures and the analysis of the interaction among different-scale structures during the fabrication processes. Well-designed microstructure...This paper presents the fabrication of squama-shape micro/nano multi-scale structures and the analysis of the interaction among different-scale structures during the fabrication processes. Well-designed microstructures made of inverted pyramids and V-shape grooves are fabricated by KOH wet etching. High-dense high-aspect-ratio (HAR) nanostructures are fabricated atop microstructures by an improved maskless deep reactive ion etching (DRIE) process, with an optimized recipe to form micro/nano dual-scale structures (MNDS). Due to the impact of the profile of microstructures on the shape of nanostructures, dissymmetrical (i.e., squama-shape) nanopillars have been formed on the inclined surfaces of microstructures, while the symmetrical nanopillars are formed on the horizontal surfaces with different formation velocities. Furthermore, the optical properties of MNDS are not sensitive to structural parameters of microstructures, making the sample overcome the lithography limitation of conventional processes for photo-devices. Eventually, three-level structures are fabricated by sputtering a gold thin film on the MNDS, and the profile of MNDS is selective in the deposition of gold particles, which is very useful for practical applications.展开更多
基金The National High Technology Research and Development Program of China(863 Program)(No.2006AA01Z284)
文摘This paper discusses the design of a 10 Gb/s laser diode driver implemented in SiGe BiCMOS technology. The laser diode driver is composed of an input buffer, a predriver circuit and an output current switch stage. With the current mode logic （CML） structure, the input buffer and the predriver circuit have the capability of transmission and amplification of high speed data. By employing MOS-HBT cascode structure as the output stage, the laser diode driver exhibits very high speed and efficiency working at the 10 Gb/s data rate. The core circuit is operated under a 3. 3 V supply, while the output stage is operated under 5.5 V for sufficient headroom across the laser diode. The chip occupies a die area of 600 μm × 800μm. Measurements on chip show clear electrical eye diagrams over 10 Gb/s, which can well meet the specifications defined by SDH STM64/SONET OC192 and a 10 Gb/s Ethemet eye mask. Under a 5. 5 V supply voltage, the maximum output swing is 3.0 V with a 50 12 load （the corresponding modulation current is 60 mA）, and the total power dissipation is 660 mW.
基金Project(10ZCKFGX00200) supported by the Tianjin Science and Technology Supporting Plan,ChinaProject supported by the Fundamental Research Funds for the Central Universities of China
文摘A low power 640×480 OLED-on-silicon chip design that used in microdisplay was presented. A novel pixel circuit was proposed to meet the special requirement of OLED-on-silicon. The novel pixel consists of three transistors and one capacitor （3T 1C）. It has simple structure and can effectively reduce the current glitch generated during the AC driving from 55 pA to 7.5 pA, so that it can improve the precision of grayscale of display as well as extend the lifetime of （]）LED material. Except for the pixel array, low power row driver, column driver and other functional modules were also integrated on the chip. Several techniques were adopted to reduce the power consumption and frequency requirement of the chip. Finally, a 16×3×12 resolution chip was fabricated with standard 0.35 μm CMOS process of CSM and the chip can operate correctly.
基金supported by the National Natural Science Foundation of China (Grand Nos. 91023045, 61176103)the Key Laboratory Fund(Grant No. 9140C790103110C7903)
文摘This paper presents the fabrication of squama-shape micro/nano multi-scale structures and the analysis of the interaction among different-scale structures during the fabrication processes. Well-designed microstructures made of inverted pyramids and V-shape grooves are fabricated by KOH wet etching. High-dense high-aspect-ratio (HAR) nanostructures are fabricated atop microstructures by an improved maskless deep reactive ion etching (DRIE) process, with an optimized recipe to form micro/nano dual-scale structures (MNDS). Due to the impact of the profile of microstructures on the shape of nanostructures, dissymmetrical (i.e., squama-shape) nanopillars have been formed on the inclined surfaces of microstructures, while the symmetrical nanopillars are formed on the horizontal surfaces with different formation velocities. Furthermore, the optical properties of MNDS are not sensitive to structural parameters of microstructures, making the sample overcome the lithography limitation of conventional processes for photo-devices. Eventually, three-level structures are fabricated by sputtering a gold thin film on the MNDS, and the profile of MNDS is selective in the deposition of gold particles, which is very useful for practical applications.
