Aim To present an ASIC design of DA based 2 D IDCT. Methods\ In the design of 1 D IDCT is utilized a Chen based fast IDCT algorithm, and multiplier accumulators based on distributed algorithm contributes in reduc...Aim To present an ASIC design of DA based 2 D IDCT. Methods\ In the design of 1 D IDCT is utilized a Chen based fast IDCT algorithm, and multiplier accumulators based on distributed algorithm contributes in reducing the hardware amount and in enhancing the speed performance. Results and Conclusion\ VHDL simulation, synthesis and layout design of system are implemented. This 2 D IDCT ASIC design owns best timing performance when compared with other better designs internationally. Results of design prove to be excellent.展开更多
Cloud computing is becoming a key factor in the market day by day. Therefore, many companies are investing or going to invest in this sector for development of large data centers. These data centers not only consume m...Cloud computing is becoming a key factor in the market day by day. Therefore, many companies are investing or going to invest in this sector for development of large data centers. These data centers not only consume more energy but also produce greenhouse gases. Because of large amount of power consumption, data center providers go for different types of power generator to increase the profit margin which indirectly affects the environment. Several studies are carried out to reduce the power consumption of a data center. One of the techniques to reduce power consumption is virtualization. After several studies, it is stated that hardware plays a very important role. As the load increases, the power consumption of the CPU is also increased. Therefore, by extending the study of virtualization to reduce the power consumption, a hardware-based algorithm for virtual machine provisioning in a private cloud can significantly improve the performance by considering hardware as one of the important factors.展开更多
Explaining the causes of infeasibility of Boolean formulas has many practical applications in electronic design automation and formal verification of hardware.Furthermore,a minimum explanation of infeasibility that ex...Explaining the causes of infeasibility of Boolean formulas has many practical applications in electronic design automation and formal verification of hardware.Furthermore,a minimum explanation of infeasibility that excludes all irrelevant information is generally of interest.A smallest-cardinality unsatisfiable subset called a minimum unsatisfiable core can provide a succinct explanation of infea-sibility and is valuable for applications.However,little attention has been concentrated on extraction of minimum unsatisfiable core.In this paper,the relationship between maximal satisfiability and mini-mum unsatisfiability is presented and proved,then an efficient ant colony algorithm is proposed to derive an exact or nearly exact minimum unsatisfiable core based on the relationship.Finally,ex-perimental results on practical benchmarks compared with the best known approach are reported,and the results show that the ant colony algorithm strongly outperforms the best previous algorithm.展开更多
Several fractionally spaced equalizers(FSE) which could be used in 60 GHz systems are presented in this paper. For 60 GHz systems, low-power equalization algorithms are favorable. We focus on FSE in both time domain(T...Several fractionally spaced equalizers(FSE) which could be used in 60 GHz systems are presented in this paper. For 60 GHz systems, low-power equalization algorithms are favorable. We focus on FSE in both time domain(TD) and frequency domain(FD) in order to meet different complexity requirements of 60 GHz systems. Compared with symbol spaced equalizer(SSE), FSE can relax the requirement of sampling synchronization hardware significantly. Extensive simulation results show that our equalization algorithms not only eliminate ISI efficiently, but are also robust to timing synchronization errors.展开更多
Baseband design and implementation for micro/pico base stations （mBS） in 5G ultra-dense network （UDN） is studied. Low cost is an essential requirement for mBS baseband in UDN. Digital baseband cost of ASIC/ASIP （...Baseband design and implementation for micro/pico base stations （mBS） in 5G ultra-dense network （UDN） is studied. Low cost is an essential requirement for mBS baseband in UDN. Digital baseband cost of ASIC/ASIP （Application Specific Integrated Circuit / Instruction-set processor） is of the most uncertainty in roBS system. However. the actual costs and hardware feasibility of the baseband are yet unknown to network deployers and researchers. In this paper, we studied the baseband hardware system design and implementation for low-cost roBS. We analyzed popular baseband algorithms and architectures for both full-digital and hybrid beamforming （BF） for UDN. We then proposed feasible chip-level solutions for the baseband with up to 128-antenna BS system, and estimated their implementation cost. Results show that among lull-digital BF algorithms, zero-forcing is a choice of high performance and low cost; for hybrid BF, 4×32 architecture （32 RF chains） provides good reduction in baseband cost with acceptable performance loss, thus it can be a preferable solution under low cost consider- ation. The proposed system planning method can also be used for the design of other related systems.展开更多
Before the task of autonomous underwater vehicle(AUV) was implemented actually,its semi-physical simulation system of pipeline tracking had been designed.This semi-physical simulation system was used to test the softw...Before the task of autonomous underwater vehicle(AUV) was implemented actually,its semi-physical simulation system of pipeline tracking had been designed.This semi-physical simulation system was used to test the software logic,hardware architecture,data interface and reliability of the control system.To implement this system,the whole system plan,including interface computer and the methods of pipeline tracking,was described.Compared to numerical simulation,the semi-physical simulation was used to test the real software and hardware more veritably.In the semi-physical simulation system,tracking experiments of both straight lines and polygonal lines were carried out,considering the influence of ocean current and the situation of buried pipeline.The experimental results indicate that the AUV can do pipeline tracking task,when angles of pipeline are 15°,30°,45° and 60°.In the ocean current of 2 knots,AUV could track buried pipeline.展开更多
In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented alg...In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8x8 block. The proposed architecture works in a parallel way and is simulated by Modelsirn 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 FPGA device. The implementation results show that this architecture can achieve 190 MHz and 10 clock cycles are reduced to complete the entire interpolation process when compared with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.展开更多
文摘Aim To present an ASIC design of DA based 2 D IDCT. Methods\ In the design of 1 D IDCT is utilized a Chen based fast IDCT algorithm, and multiplier accumulators based on distributed algorithm contributes in reducing the hardware amount and in enhancing the speed performance. Results and Conclusion\ VHDL simulation, synthesis and layout design of system are implemented. This 2 D IDCT ASIC design owns best timing performance when compared with other better designs internationally. Results of design prove to be excellent.
基金supported by the National Research Foundation (NRF) of Korea through contract N-14-NMIR06
文摘Cloud computing is becoming a key factor in the market day by day. Therefore, many companies are investing or going to invest in this sector for development of large data centers. These data centers not only consume more energy but also produce greenhouse gases. Because of large amount of power consumption, data center providers go for different types of power generator to increase the profit margin which indirectly affects the environment. Several studies are carried out to reduce the power consumption of a data center. One of the techniques to reduce power consumption is virtualization. After several studies, it is stated that hardware plays a very important role. As the load increases, the power consumption of the CPU is also increased. Therefore, by extending the study of virtualization to reduce the power consumption, a hardware-based algorithm for virtual machine provisioning in a private cloud can significantly improve the performance by considering hardware as one of the important factors.
基金the National Natural Science Foundation of China (No.60603088)
文摘Explaining the causes of infeasibility of Boolean formulas has many practical applications in electronic design automation and formal verification of hardware.Furthermore,a minimum explanation of infeasibility that excludes all irrelevant information is generally of interest.A smallest-cardinality unsatisfiable subset called a minimum unsatisfiable core can provide a succinct explanation of infea-sibility and is valuable for applications.However,little attention has been concentrated on extraction of minimum unsatisfiable core.In this paper,the relationship between maximal satisfiability and mini-mum unsatisfiability is presented and proved,then an efficient ant colony algorithm is proposed to derive an exact or nearly exact minimum unsatisfiable core based on the relationship.Finally,ex-perimental results on practical benchmarks compared with the best known approach are reported,and the results show that the ant colony algorithm strongly outperforms the best previous algorithm.
基金supported in part by the National High Technology Research and Development Program of China(863 Program)(No.2011AA010201)National Science and Technology Major Project(No.2013ZX03005010)+1 种基金the National Natural Science Foundation of China(NSFC)(No.61371103 and No.60902025)Key Science and Technology Program of Sichuan Province of China(No.2012FZ0119 and No.2012FZ0029)
文摘Several fractionally spaced equalizers(FSE) which could be used in 60 GHz systems are presented in this paper. For 60 GHz systems, low-power equalization algorithms are favorable. We focus on FSE in both time domain(TD) and frequency domain(FD) in order to meet different complexity requirements of 60 GHz systems. Compared with symbol spaced equalizer(SSE), FSE can relax the requirement of sampling synchronization hardware significantly. Extensive simulation results show that our equalization algorithms not only eliminate ISI efficiently, but are also robust to timing synchronization errors.
基金supporting from National High Technical Research and Development Program of China(863 program)2014AA01A705 is sincerely acknowledged by authors
文摘Baseband design and implementation for micro/pico base stations （mBS） in 5G ultra-dense network （UDN） is studied. Low cost is an essential requirement for mBS baseband in UDN. Digital baseband cost of ASIC/ASIP （Application Specific Integrated Circuit / Instruction-set processor） is of the most uncertainty in roBS system. However. the actual costs and hardware feasibility of the baseband are yet unknown to network deployers and researchers. In this paper, we studied the baseband hardware system design and implementation for low-cost roBS. We analyzed popular baseband algorithms and architectures for both full-digital and hybrid beamforming （BF） for UDN. We then proposed feasible chip-level solutions for the baseband with up to 128-antenna BS system, and estimated their implementation cost. Results show that among lull-digital BF algorithms, zero-forcing is a choice of high performance and low cost; for hybrid BF, 4×32 architecture （32 RF chains） provides good reduction in baseband cost with acceptable performance loss, thus it can be a preferable solution under low cost consider- ation. The proposed system planning method can also be used for the design of other related systems.
基金Projects(50909025,51179035) supported by the National Natural Science Foundation of ChinaProject(HEUCFZ1003) supported by the Fundamental Research Funds for Central Universities of China
文摘Before the task of autonomous underwater vehicle(AUV) was implemented actually,its semi-physical simulation system of pipeline tracking had been designed.This semi-physical simulation system was used to test the software logic,hardware architecture,data interface and reliability of the control system.To implement this system,the whole system plan,including interface computer and the methods of pipeline tracking,was described.Compared to numerical simulation,the semi-physical simulation was used to test the real software and hardware more veritably.In the semi-physical simulation system,tracking experiments of both straight lines and polygonal lines were carried out,considering the influence of ocean current and the situation of buried pipeline.The experimental results indicate that the AUV can do pipeline tracking task,when angles of pipeline are 15°,30°,45° and 60°.In the ocean current of 2 knots,AUV could track buried pipeline.
文摘In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8x8 block. The proposed architecture works in a parallel way and is simulated by Modelsirn 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 FPGA device. The implementation results show that this architecture can achieve 190 MHz and 10 clock cycles are reduced to complete the entire interpolation process when compared with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.
