The authors will focus on the study of the design of Multiprocessor Systems on Chip （MPSoC）, specifically in the context of improving the performance of applications located on the MPSoC architecture. The objective ...The authors will focus on the study of the design of Multiprocessor Systems on Chip （MPSoC）, specifically in the context of improving the performance of applications located on the MPSoC architecture. The objective of this research is to study the problems of transition from a pure software implementation for an embodiment admitting one or more hardware components and to develop a methodology for automatic generation of migration of a software task into a hardware component in MPSoC. The transformation of a software task into a hardware task led to many changes, hardware part （connection, the requirement of an interrupt controller...）, software part （at least one task, I/O （I/O）, synchronization...） and an architectural point of view, the remarkable aspects of data storage. The experiment is done on the MJPEG decoder to illustrate the effectiveness of the authors＇ tool for automatic generation of migration.展开更多
The paper proposes a novel hardware-based private information retrieval （HWPIR） protocol. By partially reshuffling previously accessed items in each round, instead of frequently reshuffling the whole database, the s...The paper proposes a novel hardware-based private information retrieval （HWPIR） protocol. By partially reshuffling previously accessed items in each round, instead of frequently reshuffling the whole database, the scheme makes better use of shuffled data copies and achieves the computation overhead at O（/N/K）,where N and k are the sizes of the database and secure storage respectively. For securestorage with moderate size, e.g. k = O（/N）, the overhead is 0（4/N）. The result is much better than the state-of-art schemes （as compared to e.g. O（log2N））. Without increasing response time and communication cost, the proposed protocol is truly practicable regardless of the database size. The security and preformance of the protocol is formally analyzed.展开更多
Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Di...Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Distance model and the model based on the template value of power consumption in combinational logic circuit. The new model can describe the power consumption characteristics of sequential logic circuits and those of combinational logic as well. The new model can be used to improve the existing power analysis methods and detect the information leakage of power consumption. Experimental results show that, compared to CPA（Correlation Power Analysis） method, our proposed attack which adopt the combinational model is more efficient in terms of the number of required power traces.展开更多
文摘The authors will focus on the study of the design of Multiprocessor Systems on Chip （MPSoC）, specifically in the context of improving the performance of applications located on the MPSoC architecture. The objective of this research is to study the problems of transition from a pure software implementation for an embodiment admitting one or more hardware components and to develop a methodology for automatic generation of migration of a software task into a hardware component in MPSoC. The transformation of a software task into a hardware task led to many changes, hardware part （connection, the requirement of an interrupt controller...）, software part （at least one task, I/O （I/O）, synchronization...） and an architectural point of view, the remarkable aspects of data storage. The experiment is done on the MJPEG decoder to illustrate the effectiveness of the authors＇ tool for automatic generation of migration.
文摘The paper proposes a novel hardware-based private information retrieval （HWPIR） protocol. By partially reshuffling previously accessed items in each round, instead of frequently reshuffling the whole database, the scheme makes better use of shuffled data copies and achieves the computation overhead at O（/N/K）,where N and k are the sizes of the database and secure storage respectively. For securestorage with moderate size, e.g. k = O（/N）, the overhead is 0（4/N）. The result is much better than the state-of-art schemes （as compared to e.g. O（log2N））. Without increasing response time and communication cost, the proposed protocol is truly practicable regardless of the database size. The security and preformance of the protocol is formally analyzed.
基金supported by Major State Basic Research Development Program(No. 2013CB338004)National Natural Science Foundation of China(No.61402286, 61202372,61202371,61309021)National Science and Technology Major Project of the Ministry of Science and Technology of China (No.2014ZX01032401-001)
文摘Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Distance model and the model based on the template value of power consumption in combinational logic circuit. The new model can describe the power consumption characteristics of sequential logic circuits and those of combinational logic as well. The new model can be used to improve the existing power analysis methods and detect the information leakage of power consumption. Experimental results show that, compared to CPA（Correlation Power Analysis） method, our proposed attack which adopt the combinational model is more efficient in terms of the number of required power traces.
