硅低速刻蚀和钨膜刻蚀研究

针对半导体器件研制过程中等离子体刻蚀工艺的具体需要 ,研究了硅的低速率刻蚀和钨薄膜的刻蚀 .得到了加磁场条件下刻蚀速率与刻蚀气体流量、射频功率的关系曲线 .得到了不加磁场时不同刻蚀气体流量下钨的刻蚀速率 ,以及在刻蚀气体中掺杂不同比例氧气时硅的刻蚀速率 .对上述结果加以简单的讨论并给出了符合工艺要求的刻蚀条件 .

Optimization of Plasma Etching Parameters and Mask for Silica Optical Waveguides

Optical waveguides in silica-on-silicon are one of the key elements in optical communications.The processes of deep etching silica waveguides using resist and metal masks in RIE plasma are investigated.The etching responses,including etching rate and selectivity as functions of variation of parameters,are modeled with a 3D neural network.A novel resist/metal combined mask that can overcome the single-layer masks’ limitations is developed for enhancing the waveguides deep etching and low-loss optical waveguides are fabricated at last.

Fabrication of Ultra Deep Electrical Isolation Trenches with High Aspect Ratio Using DRIE and Dielectric Refill

A novel technique to fabricate ultra deep high aspect ratio electrical isolation trenches with DRIE and dielectric refill is presented.The relationship between trench profile and DRIE parameters is discussed.By optimizing DRIE parameters and RIE etching the trenches’ opening,the ideal trench profile is obtained to ensure that the trenches are fully refilled without voids.The electrical isolation trenches are 5μm wide and 92μm deep with 0.5μm thick oxide layers on the sidewall as isolation material.The measured I-V result shows that the trench structure has good electrical isolation performance:the average resistance in the range of 0～100V is more than 10 11Ω and no breakdown appears under 100V.This isolation trench structure has been used in fabrication of the bulk integrated micromachined gyroscope,which shows high performance.

Experimental Study on the Footing Effect for SOG Structures Using DRIE

This paper experimentally studies the effects of the conductivity of a silicon wafer and the gap height between silicon structures and glass substrate on the footing effect for silicon on glass （SOG） structures in the deep reactive ion etching （DRIE） process. Experiments with gap heights of 5,20, and 50μm were carried out for performance comparison of the footing effect. Also,two kinds of silicon wafers with resistivity of 2-4 and 0.01-0. 0312Ω· cm were used for the exploration. The results show that structures with resistivity of 0.01 - 0. 0312Ω· cm have better topography than those with resistivity of 2-4Ω· cm; and structures with 50μm-high gaps between silicon structures and glass substrate suffer some- what less of a footing effect than those with 20μm-high gaps,and much less than those with Stem-high gaps. Our theoretical analysis indicates that either the higher conductivity of the silicon wafer or a larger gap height between silicon structures and glass substrate can suppress footing effects. The results can contribute to the choice of silicon type and optimum design for many microsensors.

Reactive Ion Etching of GaAs,GaSb,InP and InAs in Cl_2/Ar Plasma

Reactive ion etching characteristics of GaAs,GaSb,InP and InAs using Cl2/Ar plasma have been investigated,it is that,etching rates and etching profiles as functions of etching time,gas flow ratio and RF power.Etch rates of above 0.45 μm/min and 1.2 μm/min have been obtained in etching of GaAs and GaSb respectively, while very slow etch rates （<40 nm/min） were observed in etching of In-containing materials,which were linearly increased with the applied RF power.Etched surfaces have remained smooth over a wide range of plasma conditions in the etching of GaAs,InP and InAs,however,were partly blackened in etching of GaSb due to a rough appearance.

Fabrication of low-loss SiO2/Si channel waveguides by roughness reduction

An experimental study of the dependence of SiO2 waveguide side wall roughness on the etch condi- tions and etch masks in CHF3/O2 based reactive ion etching plasma was reported. When working under standard low-pressure （20mtorr） etching conditions, a novel etch roughening phenomenon has been observed in the plasma, that is, the roughness of the etched front surface increases with the amount of material etched, independent of etch rate, RF power, and gas composition. Besides, the etched underlying side wall will be tapered as the upper SU-8 resist pattern degradation transfers downward. A process using double-layered mask, consisting of SU-8 resist and thin Chromium film, was developed for improving the side wall smoothness. Based on the studies, SiO2/Si channel waveguides with the propagation loss less than 0. 07dB/cm were fabricated at last.

Nanotechnology:fundamental research to product development

The concept of an integrated "lab on a chip" has long been a goal for the micro-electro-mechanical-systems(MEMS) community.This would entail the integration of not only the sampling and analysis of various functions,but also the ability to transmit this information off the chip to a central repository.This paper describes the initial steps in the fabrication of a "lab on a chip" which would continually analyze blood sampled via microneedles using techniques such as nano plasmonics,specifically,concentrations of glucose.The analysis could then be transmitted off the chip using digital signal processing.This paper describes the analysis and optimization of the microneedle shape and size and the fabrication of the resulting needles in silicon using deep reactive ion etching(DRIE).The paper also describes the opportunities for fabrication of such needles in alternative materials and describes the issues that still have to be overcome before such an integrated device is realized.

A New Approach to Cleave MEMS Devices from Silicon Substrates

Dicing of fabricated MEMS （microelectromechanical system） devices is sometimes a source of challenge, especially when devices are overhanging structures. In this work, a modified cleaving technique is developed to precisely separate fabricated devices from a silicon substrate without requiring a dicing machine. This technique is based on DRIE （deep reactive ion etching） which is regularly used to make cleaving trenches in the substrate during the releasing stage. Other similar techniques require some extra later steps or in some cases a long HF soak. To mask the etching process, a thick photoresist is used. It is shown that by applying different UV （ultraviolate） exposure and developing times for the photoresist, the DRIE process could be controlled to etch specific cleaving trenches with less depth than other patterns on the photoresist. Those cleaving trenches are used to cleave the wafer later, while the whole wafer remains as one piece until the end of the silicon etching despite some features being etched all the way through the wafer at the same time. The other steps of fabricating and releasing the devices are unaffected. The process flow is described in details and some results of applying this technique for cleaving fabricated cantilevers on a silicon substrate are presented.

Preparation and characterization of three-dimensional micro-electrode for micro-supercapacitor based on inductively coupled plasma reactive etching technology

The capacity of supercapacitor charge storage depends on the size of the electrode surface area and the active material on the electrodes.To enhance the charge storage capacity with a reduced volume,silicon is used as the electrode material,and three-dimensional electrode structure is prepared to increase the electrode surface area on the footprint area by inductively coupled plasma reactive etching(ICP) techniques.The anodic constant current deposition method is employed to deposit manganese oxide on the electrode surface as the electroactive material.For comparison,samples without slot are prepared with a two-dimensional electrode.Scanning Electron Microscopy(SEM) and Energy Dispersive Spectroscopy(EDS) are used to characterize the surface morphology of the electrode structure and the deposited electroactive material.Electrochemical properties of the electrode are characterized by the cyclic voltammetry(CV) and the constant current charge-discharge method.Experimental results show that our approach can effectively increase the electrode surface area with more electroactive substances,and hence can increase storage capacity of the micro-supercapacitor.

Formation mechanism of multi-functional black silicon based on optimized deep reactive ion etching technique with SF_6/C_4F_8

This paper reports a controllable multi-functional black silicon surface with nanocone-forest structures fabricated by an optimized deep reactive ion etching(DRIE)technique using SF6/C4F8 in cyclic etching-passivation process,which is maskless,effective and controllable.The process conditions are investigated by systematically comparative experiments and core parameters have been figured out,including etching process parameters,pre-treatment,patterned silicon etching and inclined surface etching.Based on the experimental data,the formation mechanism of nanocone shape is developed,which provides a novel view for in-depth understanding of abnormal phenomena observed in the experiments under different process situations.After the optimization of the process parameters,the black silicon surfaces exhibit superhydrophobicity with tunable reflectance.Additionally,the quantitative relationship between nanocones aspect ratio and surface reflectance and static contact angle is obtained,which demonstrates that black silicon surfaces with unique functional properties(i.e.,cross-combination of reflectance and wettability)can be achieved by controlling the morphology of nanostructures.

Fabrication and characterization of squama-shape micro/nano multi-scale silicon material

This paper presents the fabrication of squama-shape micro/nano multi-scale structures and the analysis of the interaction among different-scale structures during the fabrication processes. Well-designed microstructures made of inverted pyramids and V-shape grooves are fabricated by KOH wet etching. High-dense high-aspect-ratio (HAR) nanostructures are fabricated atop microstructures by an improved maskless deep reactive ion etching (DRIE) process, with an optimized recipe to form micro/nano dual-scale structures (MNDS). Due to the impact of the profile of microstructures on the shape of nanostructures, dissymmetrical (i.e., squama-shape) nanopillars have been formed on the inclined surfaces of microstructures, while the symmetrical nanopillars are formed on the horizontal surfaces with different formation velocities. Furthermore, the optical properties of MNDS are not sensitive to structural parameters of microstructures, making the sample overcome the lithography limitation of conventional processes for photo-devices. Eventually, three-level structures are fabricated by sputtering a gold thin film on the MNDS, and the profile of MNDS is selective in the deposition of gold particles, which is very useful for practical applications.

A single-mask dry-release process for fabrication of high aspect ratio SOI MEMS devices

A single-mask dry-release process for fabrication of high aspect ratio SOI MEMS devices is presented,which takes advantage of the lag effect in silicon DRIE(deep reactive ion etching).The wide trenches and the releasing holes are etched to the buried oxide in the first-step DRIE whereas the narrow trenches are still connected due to the lag effect.After the buried oxide is removed by wet etching through the opened releasing holes and wide trenches,the narrow trenches are etched through by the second-step DRIE.Not only can the sticking problems be avoided,but also the footing effect during the DRIE can be partially suppressed.The feasibility of the proposed technique was verified by implementing a capacitive accelerometer.The scale factor and the non-linearity of the fabricated accelerometer were measured to be 63.4 mV/g and 0.1% with the measurement range of ±1 g,respectively.