This paper introduces two kinds of sequences used in spread spectrum communication system： pseudo-noise （PN） se-quence generated by linear feedback shift register（LFSR）, such as m-sequence and Gold sequence...This paper introduces two kinds of sequences used in spread spectrum communication system： pseudo-noise （PN） se-quence generated by linear feedback shift register（LFSR）, such as m-sequence and Gold sequence, and the chaotic sequence generated by the determination of the nonlinear system. The characteristics of PN sequence and chaotic sequence are analyzed by simulation, and the advantages and disadvantages of different sequences in spread spectrum communication system are ob-tained. The advantages of sequence can be used to improve signal transmission in a spread spectrum communication system.展开更多
Prior group-based fingerprinting achieves better detection performance when colluders are from the same group. But in digital wholesale and needs to be identified retail, the middleman as well as customers especially ...Prior group-based fingerprinting achieves better detection performance when colluders are from the same group. But in digital wholesale and needs to be identified retail, the middleman as well as customers especially against group colluding attack. The group tracing is neglected in previous works. In this paper, we propose a novel multimedia group fingerprint to trace malicious middlemen along with customers. We explore the quality of the non degenerate linear shift register sequence （NDLSRS） which is convenient in group initialization and management. The theoretic analysis and simulation experiment results show that NDLSRS has good resistance against attacks from colluding groups/ members even after its volume expanded.展开更多
A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm ...A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.展开更多
Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback sh...Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.展开更多
基金National Natural Science Foundation of China(No.61471325)
文摘This paper introduces two kinds of sequences used in spread spectrum communication system： pseudo-noise （PN） se-quence generated by linear feedback shift register（LFSR）, such as m-sequence and Gold sequence, and the chaotic sequence generated by the determination of the nonlinear system. The characteristics of PN sequence and chaotic sequence are analyzed by simulation, and the advantages and disadvantages of different sequences in spread spectrum communication system are ob-tained. The advantages of sequence can be used to improve signal transmission in a spread spectrum communication system.
文摘Prior group-based fingerprinting achieves better detection performance when colluders are from the same group. But in digital wholesale and needs to be identified retail, the middleman as well as customers especially against group colluding attack. The group tracing is neglected in previous works. In this paper, we propose a novel multimedia group fingerprint to trace malicious middlemen along with customers. We explore the quality of the non degenerate linear shift register sequence （NDLSRS） which is convenient in group initialization and management. The theoretic analysis and simulation experiment results show that NDLSRS has good resistance against attacks from colluding groups/ members even after its volume expanded.
文摘A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.
基金Foundation items:Fundamental Research Funds for the Central Universities(No.JUSRP51510)Primary Research&Development Plan of Jiangsu Province(No.BE2019003-2)。
文摘Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.
