一种高频片内CMOS平衡运算放大器

本文设计和研制了具有稳定共模反馈电路的高频片内CMOS平衡运算放大器。电路用3μmN-WELL CMOS硅栅工艺实现,提高了增益、带宽、电压抑制比等性能。并对电路进行理论分析,提出了平衡运算放大器的小信号和电压抑制比的分析模型,给出了工艺和实验结果。

理想运算放大电路的等效分析

以运算放大电路为分析对象,通过分析指出,传统的虚短路、虚断路分析方法在处理较复杂电路时比较繁琐.提出定义一个零电源替代运算放大器,使电路等效简化.等效后的电路可容易地运用KCL,KVL,节点法,网孔法进行分析.

低噪声高单位增益带宽双极型运放设计

设计了一款低噪声、高单位增益带宽的运放电路。该款电路基于0.25μm SiGe双极工艺,采用三级级联的形式,输入级选取多个双极型晶体管(BJT)并联,用作差分对管,以抑制噪声;中间级不但用pnp型BJT镜像电流源作为有源负载,而且并联多个横向pnp型BJT用以提升单位增益带宽;输出级则设计成低电容输入和低电容输出方式,借此拓展带宽。对所设计的运放电路进行了PSPICE仿真及硬件电路实验。结果表明,当电源电压为2.5 V时,运放电路的实测交流开环电压增益为80 dB,开环相位裕度为61.5°,单位增益带宽为203 MHz,在10 kHz处的输入电压噪声密度仅为1.2 nV/Hz^(1/Hz),因而可用于低噪声、高单位增益带宽的片上相位噪声测量电路和微波功率传感器等系统的设计中。

Single Event Transients of Operational Amplifier and Optocoupler

The single event transient effects of the operational amplifier LM124J and the optocoupler HCPL 5231 are investigated by a pulsed laser test facility. The relation of transient pulse shape to pulsed laser equivalent LET is tested,the sensitive areas of the SET effects are identified in voltage follower application mode of LM124J, and the mechanism is initially analyzed. The transient amplitude and duration of HCPL5231 at various equivalent LET are examined,and the SET cross-section is measured. The results of our test and heavy ion experimental data coincide closely,indicating that a pulsed laser test facility is a valid tool for single event effect evaluation.

Design of an OP-AMP Based on a LDO Regulator

An operational amplifier （OP-AMP） with a ground current of about 0.6μA is presented. Moreover, this amplifier reaps the benefits of incorporating a foldback current limiting circuit,which enables the low-dropout voltage regulator without the need of a special current limiting subblock. Therefore,the object of ultra-low power is realized because of a great reduction in transistors and current limbs.

A 59mW 10b 40Msample/s Pipelined ADC

This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter （ADC） fabricated in a 0.25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is realized using just four amplifiers with a separate sample-and-hold block. It employs two key techniques： a high bandwidth low-power gain-boosting telescopic amplifiers technique and a low power low offset dynamic comparators technique.The ADC achieves a 8.1 effective number of bits,a maximum differential nonlinearity of a 0.85 least significant bit（LSB）, and maximum integral nonlinearity of 2.2LSB for a 0.5MHz input at full sampling rate. It occupies 1.24mm^2 ,which also includes a bandgap and a voltage reference circuit and dissipates only 59mW.

A High Precision CMOS Opamp Suitable for ISFET Readout

This paper presents a high precision CMOS opamp suitable for ISFET readout. The opamp is tailored to provide a constant bias condition for ISFET as part of the readout circuits and,hence,is compatible for single chip integration with the sensor. A continuous time auto-zero stabilization technique is studied and employed, with the aim of suppressing the low frequency noises, including the offset voltage, 1/f noise, and temperature drift. The design is based on a 0.35μm CMOS process. With a 3.3V power supply,it maintains a DC open loop gain of more than 100dB and an offset voltage of around 11μV,while the overall power dissipation is only 1.48mW. With this opamp, a pH microsensor is constructed, of which the functionality is verified by experimental tests.

An Accelerated Simulation Method for ELDRS of Bipolar Operational Amplifiers Using a Dose-Rate Switching Experiment

Through different dose-rate switching evaluation methods,the radiation-response rules of operational amplifiers are studied when the irradiation dose rate is switched from high to low under different radiation temperatures and total doses. The experimental results indicate that the response characteristics could be affected by the switching total doses, irradiation temperatures,and dose rates individually or together. Accelerated evaluation on the ELDRS can be realized by adopting a proper dose-rate switching method. Meanwhile, the irradiation time can also be reduced. Finally, the mechanisms of the difference between various radiation responses are analyzed.

A Novel Charge-Transfer Matching Cell for High-Precision Correlation and Low-Power

A novel matching cell circuitry using charge transfer circuit technique for high precision correlation calculation is presented.The cell calculates the absolute value of the difference between two analog input voltages and amplifies the result.Amplification gain can be designed by the capacitance size in the cell and threshold voltage mismatch can be canceled automatically,thus high precision operation of the circuit is achieved.The circuit can be operated with low power dissipation of about 12μW at a frequency of 50MHz.Because of its simple structure and small silicon area,the matching cell is suitable to realize the correlation dealing with many template vectors that have many elements in a chip.

CD-ROM/DVD马达驱动电路的设计与开发

本文介绍了一种CD-ROM/DVD马达驱动IC的设计和简洁地介绍了其职能。为例AM5954,本文给出了主要功能模块的电压基准的工作原理,热保护电路,当前的传输电路和级联与数学推导运算放大器。委员会还讨论了布局设计,尤其是困难和一个马达驱动集成电路布图设计的重点,提供相应的解决方案。

An 80dB Dynamic Range ΣΔ Modulator for Low-IF GSM Receivers

A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.

功率取样系统中巧用A／D转换器

本文从A／D转换器本身的特点出发，结合运算放大器及单片机的使用，对变步长功率取样系统的设计思路进行了阐述。

Novel hybrid optimal algorithm for broad-band Raman amplifier

A hybrid optimal algorithm, named the SAA-PA in brief, based on the simulated annealing algorithm （SAA） and the Powell algorithm （PA） is proposed. The proposed algorithm puts the random search strategy of the SAA into the PA, which can prevent optimizing courses from trapping in local optima. The SAA-PA can effectively solve multimodal optimization in the distributed multi-pump Raman amplifier （DMRA）. Optimal results show that, under the conditions of the on-off gain of 10 dB, the gain bandwidth of larger than 80 nm and the fiber length of 80 km, the gain ripple of less than 1.25 dB can be designed from the DMRA with only four backward pumps after the optimization of the proposed SAA-PA. Compared with the pure SAA, the SAA-PA can attain a lower gain ripple with the same number of pumps. Also, the relationship between the optimal signal bandwidth and the number of pumps can be simulated numerically with the SAA-PA.

Analysis and design of high linearity current reference for current mode circuits

A complementary metal-oxide-semiconductor transistor （CMOS） voltage-to-current（VTC）converter with high linearity for current-mode analog and digital integrated circuits is described. A high gain operational amplifier （OPA） is utilized to form negative feedback. A proportional to absolute temperature （PTAT） current reference with transistors operated in a weak inversion is used as the bias circuit. The resistor and the OPA nonlinearity behavior are analyzed in detail. By optimizing parameters in OPA and adopting a small voltage coefficient polysilicon resistor as a linear device, a high linearity is achieved. The circuit is implemented in a standard 0. 6 μm CMOS technology. The low frequency gain of the OPA exceeds 90 dB. The test results indicate that the total harmonic distortion （THD）is 0. 000 2%. The common-mode input linearity range is 0 to 2. 6 V. Correspondingly, the output current range is 50 to 426μA. The sensitivity of the PTAT current reference to Vdd is approximately 0. 021 7. The chip consumes a power of less than 1.3 mW for a 5 V supply, and occupies an area of 0. 112 mm^2.

An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

AN INVESTIGATION OF RETINEX ALGORITHMS FOR IMAGE ENHANCEMENT

This letter introduces color constancy and Retinex theory for image enhancement.It clas- sifies Retinex algorithms into four categories and provides their principles and implementations in general.The experimental results of Frankle-McCann,MSR (Multi-Scale Retinex) and PNSD (Pro- jected Normalized Steepest Descent) Retinex algorithms are presented and compared.Moreover, variance and average gradient are proposed to evaluate the performance of the different algorithms.

“Eigen-Operator” Method of the Square of Schroedinger Operator in Interaction Picture and Its Application in Describing Parametric Amplifiers

We extend the method of searching “eigen-operator” of the square of the Schroedinger operator to the interaction picture, which not only helps to construct Hamiltonians of two kinds of parametric amplifiers but also leads to a new uncertainty relation regarding to the free Hamiltonian and the interacting Hamiltonian.

Fully Differential Leapfrog Implementation for High-Pass Ladder Filters

This paper presents a novel leapfrog signal flow graph （SFG） implementation by fully differential Op amp integrators, which combines low sensitivity, high dynamic range with simple circuit configuration. The direct SFG simulation and leapfrog SFG simulation can yield integrator-based structures likewise, but both of them will lead to higher circuit complexity, noise density and sensitivity. Three Butterworth 5-order high-pass filters with a pass band edge frequency of 1.778 kHz are designed based on different SFGs. From the example, the noise density of the sim- plest leapfrog configuration is approximately 0.4 nV/Hz~/2 lower than those of the other two in the stop band, and shows the best noise density in the pass band. The sensitivity densities of two types of leapfrog filters are approxi- mately equivalent, while that of the direct SFG simulation filter is much higher. However, the pass band response of the simplest configuration is not as good as those of the other two because of two parasitic zeros （at 708 kHz, -31.6 dB and 1.59 MHz, 20.55 dB） and a parasitic pole （at 4.57 MHz, 45.5 dB）.

Design of Pipelined ADC Using Op Amp Sharing Technique

This paper presents a 10-bit 20 MS/s pipelined Analog-to- Digital Converter（ADC） using op amp sharing approach and removing Sample and Hold Amplifier（SHA） or SHA-less technique to reach the goal of low-power constanpfion. This design was fabricated in TSMC 0.18 wn 1P6M technology. Measurement results show at supply voltage of 1.8 V, a SFDR of 42.46 dB, a SNDR of 39.45 dB, an ENOB of 6.26, and a THDof41.82 dB are at 1 MHz sinusoidal sig- nal input. In addition, the DNL and INL are 1.4 LSB and 3.23 LSB respectively. The power onstmaption is 28.8 mW. The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.

Energy efficiency enhancement of two-way amplifier forward relaying with channel estimation error

In order to save energy consumption of two-way amplifier forward(AF) relaying with channel estimation error, an energy efficiency enhancement scheme is proposed in this work. Firstly, through the analysis of two-way AF relaying mode with channel estimation error, the resultant instantaneous SNRs at end nodes is obtained. Then, by using a high SNR approximation, outage possibility is acquired and its simple closed-form expression is represented. Specially, for using the energy resource more efficiently, a low-complexity power allocation and transmission mode selection policy is proposed to enhance the energy efficiency of two-way AF relay system. Finally, relay priority region is identified in which cooperative diversity energy gain can be achieved. The computer simulations are presented to verify our analytical results, indicating that the proposed policy outperforms direct transmission by an energy gain of 3 dB at the relative channel estimation error less than 0.001. The results also show that the two-way AF relaying transmission loses the two-way AF relaying transmission loses its superiority to direct transmission in terms of energy efficiency when channel estimation error reaches 0.03.