应用于时间数字转换器的补偿校准算法及电路

文章提出一种基于相位内插型时间数字转换器(time-to-digital converter, TDC)的补偿算法及校准电路,通过该电路能有效地解决由于亚稳态和PVT(process,voltage and temperature)因素变化引起的TDC的采样错误,并且不需要额外的计数器、锁频电路或基于统计方法学的复杂结构。基于该方法的TDC电路采用CMOS 0.110μm工艺设计实现,版图面积仅为380×140μm^(2),在1.2 V电源下功耗为4.2 mW。仿真结果表明:系统分辨率为104 ps,最大微分非线性(differential nonlinearity,DNL)和积分非线性(integral nonlinearity,INL)分别为0.3、2.5 LSB,证明依据该算法的TDC电路具有良好的时间精度和线性度。

A Fast and Efficient Global Router for Congestion Optimization

An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire length model is implemented on multiprocessor,which enables the algorithm to approach feasibility of large scale problems.Timing driven model on multiprocessor and wire length model on distributed processors are also presented.The parallel algorithm greatly reduces the run time of routing.The experimental results show good speedups with no degradation of the routing quality.

MARS:A General Multilayer Area Router

Based on a ripped-up and rerouted methodology,a multilayer area detailed router is presented by using simulated evolution technique.A modified maze algorithm is also performed for the single net.

A Chip Level Thermal Analysis Algorithm Using Boundary Element Method

With the scale of integration and operation speed of modern ICs increasing,a series of thermo-related problems arise.Hot spots,which are due to the uneven distribution of heat,invalidate some functions of the chip.An algorithm is presented to calculate the profile.With the boundary element method,3D problems are converted into 2D ones,so the temperatures of both the chip surface and inner points can be calculated quickly.This algorithm can be used to evaluate the thermal quality of a definite chip.

Visual positioning of rectangular lead components based on Harris corners and Zernike moments

With the increasing necessities for reliable printed circuit board(PCB) product, there has been a considerable demand for high speed and high precision vision positioning system. To locate a rectangular lead component with high accuracy and reliability, a new visual positioning method was introduced. Considering the limitations of Ghosal sub-pixel edge detection algorithm, an improved algorithm was proposed, in which Harris corner features were used to coarsely detect the edge points and Zernike moments were adopted to accurately detect the edge points. Besides, two formulas were developed to determine the edge intersections whose sub-pixel coordinates were calculated with bilinear interpolation and conjugate gradient method. The last experimental results show that the proposed method can detect the deflection and offset, and the detection errors are less than 0.04° and 0.02 pixels.

Totally Coded Algorithm for Switched-Current Network Analysis in Frequency Domain

Based on mirror-blocks, a totally coded algorithm （TCA） for switched-current （SI） network analysis in frequency domain is presented. The algorithm is simple, available, and suitable for any swltched-current networks. A basis of analysis and design for switched-current networks via this algorithm is provided.

Research of the test generation algorithm based on search state dominance for combinational circuit

On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the E-frontier (evaluation frontier), we can prove that this algorithm can terminate unnecessary searching step of test pattern earlier than the EST algorithm through some examples, so this algorithm can reduce the time of test generation. The test patterns calculated can detect faults given through simulation.

Optimization and Synthesis of RF CMOS Polyphase Filters with Layout Considerations

A novel software tool for optimization and synthesis of RF CMOS polyhase filters(PPFs),PPFOPTIMA,is developed.In the optimization engine,genetic algorithm is adopted to avoid local optima.Experiments on PPFOPTIMA demonstrate that it is an efficient design aid for design and optimization of RF CMOS PPFs.

Inter-Circuit Fault Location Algorithm for Two-Parallel Transmission Line

A novel numerical algorithm of fault location estimation for four-line fault without ground connection involving phases from each of the parallel lines is presented in this paper. It is based on one-terminal voltage and current data. The loop and nodal equations comparing faulted phase to non-faulted phase of two-parallel lines are introduced in the fault location estimation model, in which the source impedance of a remote end is not involved. The effects of load flow and fault resistance on the accuracy of fault location are effectively eliminated, therefore a precise algorithm of locating fault is derived. The algorithm is demonstrated by digital computer simulations.

A Parallel-based Lifting Algorithm and VLSI Architecture for DWT

A novel Parallel-Based Lifting Algorithm （PBLA） for Discrete Wavelet Transform （DWT）, exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration （VLSI） architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation （CLABI）, the critical path latency of the proposed architecture is reduced by more than half from （4Tm ＋ 8Ta）to Tm ＋ 4Ta, and is competitive to that of Convolution-Based Implementation （CBI）, but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.

A new approach to test generation for combinational circuits

Aimed at the generation of high-quality test set in the shortest possible time, the test generation for combinational circuits （CC） based on the chaotic particle swarm optimization （CPSO） algorithm is presented according to the analysis of existent problems of CC test generation, and an appropriate CPSO algorithm model has been constructed. With the help of fault simulator, the test set of ISCAS＇ 85 benchmark CC is generated using the CPSO, and some techniques are introduced such as half-random generation, and simulation of undetected fauhs.with original test vector, and inverse test vector. Experimental results show that this algorithm can generate the same fault coverage and small-size test set in short time compared with other known similar methods, which proves that the proposed method is applicable and effective.

Gridless Net Routing of Integrate Circuit with Particle Swarm Optimization Algorithm

Particle swarm optimization algorithm is presented for the layout of ＂Integrate Circuit （IC）＂ design. Particle swarm optimization based on swarm intelligence is a new evolutionary computational tool and is successfully applied in function optimization, neural network design, classification, pattern recognition, signal processing and robot technology and so on. A modified algorithm is presented and applied to the layout of IC design. For a given layout plane, first of all, this algorithm generates the corresponding grid group by barriers and nets＇ ports with the thought ofgridless net routing, establishes initialization fuzzy matrix, then utilizes the global optimization character to find out the best layout route only if it exits. The results of model simulation indicate that PSO algorithm is feasible and efficient in IC layout design.

GA-BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS

In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library, a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on 1SCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective.

Automatic pipes routing based on flow loss in electromechanical product

Based on flow loss, a new automatic pipe-routing algorithm is proposed for electromechanical product in 3D space, which consists of pre-processing and optimization search. Utilizing chaos theory, a chaos grid preprocessing model （CGPM） is established to efficiently pick up the solution space and reduce the search range in the pre-processing, which simplifies the optimization search. A modified particle swarm optimization （PSO） algorithm is presented to seek for an approximate optimal trajectory in the solution space in the optimization search based on standard PSO algorithm and migration characters of people. The comparison of experiments and analysis results shows that the modified PSO algorithm is capable of preventing prematurity effectively and searching for the optimal trajectory more efficiently. Theoretical analysis proves that the modified PSO algorithm converges at global optimum. The examples show that the automatic pipe-routing algorithm based on flow loss is effective and practical for eleetromechanieal product.

Implementing kinematics computation in FPGA co-processor for a 6-DOF space manipulator

Based on the coordinate rotation digital computer(CORDIC)algorithm,the high-speed kinematicscalculation for a six degree of freedom(DOF)space manipulator is implemented in a field programmablegate array(FPGA)co-processor.A pipeline architecture is adopted to reduce the complexity and time-consumption of the kinematics calculation .The CORDIC soft-core and the CORDIC-based pipelined kine-matics calculation co-processor are described with the very-high-speed integrated circuit hardware descrip-tion language(VHDL)language and realized in the FPGA .Finally,the feasibility of the design is vali-dated in the Spartan-3 FPGA of Xilinx Inc.,and the performance specifications of FPGA co-processor arediscussed.The results show that time-consumption of the kinematics calculation is greatly reduced.

An uplink power control algorithm using traditional iterative model for cognitive radio networks

Based on the analysis of the feature of cognitive radio networks, a relevant interference model was built. Cognitive users should consider especially the problem of interference with licensed users and satisfy the signal-to-interference noise ratio （SINR） requirement at the same time. According to different power thresholds, an approach was given to solve the problem of coexistence between licensed user and cognitive user in cognitive system. Then, an uplink distributed power control algorithm based on traditional iterative model was proposed. Convergence analysis of the algorithm in case of feasible systems was provided. Simulations show that this method can provide substantial power savings as compared with the power balancing algorithm while reducing the achieved SINR only slightly, since 6% S1NR loss can bring 23% power gain. Through further simulations, it can be concluded that the proposed solution has better effect as the noise power or system load increases.

Online model identification of lithium-ion battery for electric vehicles

In order to characterize the voltage behavior of a lithium-ion battery for on-board electric vehicle battery management and control applications,a battery model with a moderate complexity was established.The battery open circuit voltage (OCV) as a function of state of charge (SOC) was depicted by the Nernst equation.An equivalent circuit network was adopted to describe the polarization effect of the lithium-ion battery.A linear identifiable formulation of the battery model was derived by discretizing the frequent-domain description of the battery model.The recursive least square algorithm with forgetting was applied to implement the on-line parameter calibration.The validation results show that the on-line calibrated model can accurately predict the dynamic voltage behavior of the lithium-ion battery.The maximum and mean relative errors are 1.666% and 0.01%,respectively,in a hybrid pulse test,while 1.933% and 0.062%,respectively,in a transient power test.The on-line parameter calibration method thereby can ensure that the model possesses an acceptable robustness to varied battery loading profiles.

Development of a Genetic Algorithm for Evaluating the Performance of Overhead Power Distribution Lines and Proposing Solutions to Improve Distribution Line Safety

This paper aims to present and discuss the use of a power flow methodology based on Gauss elimination method to evaluate the performance of distribution network taking into account the neutral conductor absence at specific sections, and a development of a methodology based on GA （genetic algorithm） capable of evaluating alternative solutions in different bars of the feeder, in order to propose appropriate solutions to improve the distribution network safety. Besides the technical aspects, the proposed GA methodology takes into account the economic feasibility analysis. The results of power flow simulations have shown that the presence of single-phase transformers along with the absence of the neutral conductor at specific sections of the MV （medium voltage） network may increase the Vng （neutral-to-ground voltage） levels of the feeders involved, jeopardizing the system＇s safety. On the other hand, the solutions proposed by the GA methodology may reduce the network Vng levels and improve the safety conditions, providing values close to the ones found before the neutral conductor theft.

Research on the Natural Image Classification and Segmentation Algorithm based on GPU and Neural Network

In this paper, we conduct research on the natural image classification and segmentation algorithm based on GPU and neural network. The application of image segmentation is very broad, almost appeared in all areas related to image processing, and involved in various types. With the fast development of computing technology and integrated circuit technology, the renewal speed of graphics hardware. Our method combines the GPU with network to optimize the traditional image segmentation and classification methods which will be meaningful. In the future, we will focus our attention on the hardware deployment of the GPU to modify the current approach.

Low Leakage Power Sequential Circuits Using Multi-Vth at Nano-Scale Transistor

Leakage power is the dominant source of power dissipation for Sub-100 nm VLSI （very large scale integration） circuits. Various techniques were proposed to reduce the leakage power at nano-scale; one of these techniques is MTV （multi-threshold voltage） In this paper, the exact and optimal value of threshold voltage （Vth） for each transistor in any sequential circuit in the design is found, so that the value of the total leakage current in the design is at the minimum. This could be achieved by applying AI （artificial intelligence） search algorithm. The proposed algorithm is called LOAIS （leakage optimization using AI search）. LOAIS exploits the total slack time of each transistor＇s location and their contributions in the leakage current. It is introduced by AI heuristic search algorithms under 22 nm BSIM4 predictive technology model. The proposed approach saves around 80% of the sub-threshold leakage current without degrading the performance of the circuit.