In this paper, the bit synchronization algorithms in GNSS receiver are introduced, including the traditional histogram method, K-P algorithm and Viterbi algorithm. The FPGA implementation is also included. A novel tim...In this paper, the bit synchronization algorithms in GNSS receiver are introduced, including the traditional histogram method, K-P algorithm and Viterbi algorithm. The FPGA implementation is also included. A novel time division multiplexing technology （TDM） based on multi-channel shared synchronizer is proposed in this paper to solve the constrained hardware resource problem of multi-system satellite navigation receiver. Through the using of control state machine and data register structure, we realize the multiplexing of bit synchronizer of navigation receiver, which saves the hardware resource. After the experiment, it can be verified that the receiver based on the bit synchronization and multiplexing technology can correctly restore the navigation information.展开更多
Recently, trimming Soft-output Viterbi algorithm(T-SOVA) has been proposed to reduce the complexity of SOVA for Turbo codes. In its fi rst stage, a dynamic algorithm, lazy Viterbi algorithm, is used to indicate the mi...Recently, trimming Soft-output Viterbi algorithm(T-SOVA) has been proposed to reduce the complexity of SOVA for Turbo codes. In its fi rst stage, a dynamic algorithm, lazy Viterbi algorithm, is used to indicate the minimal metric differences which brings obstacle on hardware implementation. This paper proposes a Viterbi algorithm(VA) based T-SOVA to facilitate hardware implementation. In the first stage of our scheme, a modified VA with regular structure is used to fi nd the maximum likelihood(ML) path and calculate the metric differences. Further, local sorting is introduced to trim the metric differences, which reduces the complexity of trimming operation. Simulation results and complexity analysis show that VA based T-SOVA performs as well as lazy VA based T-SOVA and is easier to be applied to hardware implementation.展开更多
基金the National Natural Science Foundation of China under Grant，the China Postdoctoral Science Foundation under Grant No.2013M530526，the Fundamental Research Funds for the Central Universities under Grant No.FRF-TP-14-046A2
文摘In this paper, the bit synchronization algorithms in GNSS receiver are introduced, including the traditional histogram method, K-P algorithm and Viterbi algorithm. The FPGA implementation is also included. A novel time division multiplexing technology （TDM） based on multi-channel shared synchronizer is proposed in this paper to solve the constrained hardware resource problem of multi-system satellite navigation receiver. Through the using of control state machine and data register structure, we realize the multiplexing of bit synchronizer of navigation receiver, which saves the hardware resource. After the experiment, it can be verified that the receiver based on the bit synchronization and multiplexing technology can correctly restore the navigation information.
基金supported by NSAF under Grant(No.U1530117)National Natural Science Foundation of China(No.61471022)
文摘Recently, trimming Soft-output Viterbi algorithm(T-SOVA) has been proposed to reduce the complexity of SOVA for Turbo codes. In its fi rst stage, a dynamic algorithm, lazy Viterbi algorithm, is used to indicate the minimal metric differences which brings obstacle on hardware implementation. This paper proposes a Viterbi algorithm(VA) based T-SOVA to facilitate hardware implementation. In the first stage of our scheme, a modified VA with regular structure is used to fi nd the maximum likelihood(ML) path and calculate the metric differences. Further, local sorting is introduced to trim the metric differences, which reduces the complexity of trimming operation. Simulation results and complexity analysis show that VA based T-SOVA performs as well as lazy VA based T-SOVA and is easier to be applied to hardware implementation.
