An IGBT subcircuit model is proposed and optimized,which is fully SPICE compatible.Based on analytical equations describing the semiconductor device physics,the model parameters are extracted accurately from the measu...An IGBT subcircuit model is proposed and optimized,which is fully SPICE compatible.Based on analytical equations describing the semiconductor device physics,the model parameters are extracted accurately from the measured data without device destruction.The IGBT n - layer conductivity modulated resistor is effectively modeled as a voltage controlled resistor.The proposed model can be used to accurately predict the IGBT output I-V characteristics and low current gain etc.The simulation results are verified by the comparison with measurements and found to be in good agreement with them.The error in average is within 8%,which is better than the results of semi-mathematical models reported previously.展开更多
This paper proposes a new battery management system （BMS） based on a master-slave control mode for multi-cell li-ion battery packs. The proposed BMS can be applied in li-ion battery packs with any cell number. The w...This paper proposes a new battery management system （BMS） based on a master-slave control mode for multi-cell li-ion battery packs. The proposed BMS can be applied in li-ion battery packs with any cell number. The whole system is composed of a master processor and a string of slave manager cells （SMCs）. Each battery cell corresponds to an SMC. Unlike the conventional BMS, the proposed one has a novel method for communication, and it collects the battery status information in a direct and simple way. An SMC communicates with its adjacent counterparts to transfer the battery information as well as the commands from the master processor. The nethermost SMC communicates with the master processor directly. This method allows the battery management chips to be implemented in a standard CMOS （ complementary metal-oxide-semiconductor transistor） process. A testing chip is fabricated in the CSMC 0.5 μm 5 V N-well CMOS process. The testing results verify that the proposed method for data communication and the battery management system can protect and manage multi-cell li-ion battery packs.展开更多
A monolithic microwave integrated circuit （MMIC） power amplifier （PA） is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the...A monolithic microwave integrated circuit （MMIC） power amplifier （PA） is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the power supply and temperature, but also compensates deviations caused by the increase in input power. The bias circuit is a current-mirror configuration, and the feedback circuit helps to maintain bias voltage at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit. A shunt capacitor at the base node of the active bias transistor enhances the linearity of the PA. The chip is fabricated in an InGaP/GaAs heterojunction bipolar transistor （HBT） process. Measured results exhibit a 26. 6-dBm output compression point, 33.6% power-added efficiency （PAE） and - 40.2 dBc adjacent channel power ratio （ACPR） for wide-band code division multiple access （W-CDMA） applications.展开更多
A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade (RGC) transimpedance amplifier (TIA) is designed.The small signal circuit model of DPD is given and the bandwidth...A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade (RGC) transimpedance amplifier (TIA) is designed.The small signal circuit model of DPD is given and the bandwidth design method of a monolithic photoreceiver is presented.An important factor which limits the bandwidth of DPD detector and the photoreceiver is presented and analyzed in detail.A monolithic photoreceiver with 1.71GHz bandwidth and 49dB transimpedance gain is designed and simulated by applying a low-cost 0.6μm CMOS process and the test result is given.展开更多
Based on the fundamental relationship among the circuit power, the circuit delay and the supply voltage, four theorems associated with the application of dynamic voltage scaling （DVS） policies are proposed and prove...Based on the fundamental relationship among the circuit power, the circuit delay and the supply voltage, four theorems associated with the application of dynamic voltage scaling （DVS） policies are proposed and proved. First, the existence characteristics of the optimal supply voltage for a single task are proved, which suggests that the optimal supply voltage for the single task should be selected only within a one-dimensional term, and the corresponding task end time by the optimal supply voltage should be identical with its deadline. Then, it is pointed out that the minimum energy consumption that the DVS policy can obtain when completing a single task is certainly lower than that of the dynamic power management （DPM） policy or the combined DVS＋DPM policy under the same conditions. Finally, the theorem of energy consumption minimization for a multi-task group is proposed, which declares that it is necessary to keep the processor in the execution state during the whole task period to obtain the minimum energy consumption, while satisfying the deadline constraints of any task.展开更多
Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is ...Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.展开更多
A new,improved pixel-driving circuit is presented based on a current-programmed pixel circuit in order to achieve an AC-driving mode. This driving method realizes an AC-driving mode,removes the threshold voltage varia...A new,improved pixel-driving circuit is presented based on a current-programmed pixel circuit in order to achieve an AC-driving mode. This driving method realizes an AC-driving mode,removes the threshold voltage variation of the driving TFT due to the process variation or long-term operation,which can bring about brightness non-uniformity, and eliminates high peak pulse currents at the beginning and end of recovery time. Simulation is done with AIM-SPICE,and simulation results demonstrate that the OLED is in the reverse-biased state during recovery time.展开更多
An accurate 1.08GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process.A new convenient method of calculating oscillator period is presented.With this period calculation tech...An accurate 1.08GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process.A new convenient method of calculating oscillator period is presented.With this period calculation technique,the frequency tuning curves agree well with the experiment.At a 3.3V supply,the LC-VCO measures a phase noise of -82.2dBc/Hz at a 10kHz frequency offset while dissipating 3.1mA current.The chip size is 0.86mm×0.82mm.展开更多
A 2 5Gb/s depletion mode GaAs MESFET clock recovery and decision circuit is described,which applies to the optical fiber communication.The circuit consists of a clock recovery circuit,including a preprocessor,phase ...A 2 5Gb/s depletion mode GaAs MESFET clock recovery and decision circuit is described,which applies to the optical fiber communication.The circuit consists of a clock recovery circuit,including a preprocessor,phase detector(PD),low pass filter(LPF) and voltage controlled oscillator(VCO) and a decision circuit,including a comparator and a latch.The SPICE simulation result confirms the high frequency 2 5GHz of the clock recovery and the high speed 2 5Gb/s of the decision circuit.The 2 5Gb/s decision circuit has proved to be able to deal with the input signal and produce a digital output signal after it being sampled by a clock signal.展开更多
This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal...This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.展开更多
文摘An IGBT subcircuit model is proposed and optimized,which is fully SPICE compatible.Based on analytical equations describing the semiconductor device physics,the model parameters are extracted accurately from the measured data without device destruction.The IGBT n - layer conductivity modulated resistor is effectively modeled as a voltage controlled resistor.The proposed model can be used to accurately predict the IGBT output I-V characteristics and low current gain etc.The simulation results are verified by the comparison with measurements and found to be in good agreement with them.The error in average is within 8%,which is better than the results of semi-mathematical models reported previously.
基金The Key Science and Technology Project of Zhejiang Province(No.2007C21021)
文摘This paper proposes a new battery management system （BMS） based on a master-slave control mode for multi-cell li-ion battery packs. The proposed BMS can be applied in li-ion battery packs with any cell number. The whole system is composed of a master processor and a string of slave manager cells （SMCs）. Each battery cell corresponds to an SMC. Unlike the conventional BMS, the proposed one has a novel method for communication, and it collects the battery status information in a direct and simple way. An SMC communicates with its adjacent counterparts to transfer the battery information as well as the commands from the master processor. The nethermost SMC communicates with the master processor directly. This method allows the battery management chips to be implemented in a standard CMOS （ complementary metal-oxide-semiconductor transistor） process. A testing chip is fabricated in the CSMC 0.5 μm 5 V N-well CMOS process. The testing results verify that the proposed method for data communication and the battery management system can protect and manage multi-cell li-ion battery packs.
基金The National High Technology Research and Development Program of China(863 Program)(No.2009AA01Z260)
文摘A monolithic microwave integrated circuit （MMIC） power amplifier （PA） is proposed. It adopts a new on-chip bias circuit, which not only avoids the instability of the direct current bias caused by the change in the power supply and temperature, but also compensates deviations caused by the increase in input power. The bias circuit is a current-mirror configuration, and the feedback circuit helps to maintain bias voltage at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit. A shunt capacitor at the base node of the active bias transistor enhances the linearity of the PA. The chip is fabricated in an InGaP/GaAs heterojunction bipolar transistor （HBT） process. Measured results exhibit a 26. 6-dBm output compression point, 33.6% power-added efficiency （PAE） and - 40.2 dBc adjacent channel power ratio （ACPR） for wide-band code division multiple access （W-CDMA） applications.
文摘A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade (RGC) transimpedance amplifier (TIA) is designed.The small signal circuit model of DPD is given and the bandwidth design method of a monolithic photoreceiver is presented.An important factor which limits the bandwidth of DPD detector and the photoreceiver is presented and analyzed in detail.A monolithic photoreceiver with 1.71GHz bandwidth and 49dB transimpedance gain is designed and simulated by applying a low-cost 0.6μm CMOS process and the test result is given.
文摘Based on the fundamental relationship among the circuit power, the circuit delay and the supply voltage, four theorems associated with the application of dynamic voltage scaling （DVS） policies are proposed and proved. First, the existence characteristics of the optimal supply voltage for a single task are proved, which suggests that the optimal supply voltage for the single task should be selected only within a one-dimensional term, and the corresponding task end time by the optimal supply voltage should be identical with its deadline. Then, it is pointed out that the minimum energy consumption that the DVS policy can obtain when completing a single task is certainly lower than that of the dynamic power management （DPM） policy or the combined DVS＋DPM policy under the same conditions. Finally, the theorem of energy consumption minimization for a multi-task group is proposed, which declares that it is necessary to keep the processor in the execution state during the whole task period to obtain the minimum energy consumption, while satisfying the deadline constraints of any task.
基金The Natural Science Foundation of Jiangsu Province(No.BK2012559)Qing Lan Project of Jiangsu Province
文摘Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.
文摘A new,improved pixel-driving circuit is presented based on a current-programmed pixel circuit in order to achieve an AC-driving mode. This driving method realizes an AC-driving mode,removes the threshold voltage variation of the driving TFT due to the process variation or long-term operation,which can bring about brightness non-uniformity, and eliminates high peak pulse currents at the beginning and end of recovery time. Simulation is done with AIM-SPICE,and simulation results demonstrate that the OLED is in the reverse-biased state during recovery time.
文摘An accurate 1.08GHz CMOS LC voltage-controlled oscillator is implemented in a 0.35μm standard 2P4M CMOS process.A new convenient method of calculating oscillator period is presented.With this period calculation technique,the frequency tuning curves agree well with the experiment.At a 3.3V supply,the LC-VCO measures a phase noise of -82.2dBc/Hz at a 10kHz frequency offset while dissipating 3.1mA current.The chip size is 0.86mm×0.82mm.
文摘A 2 5Gb/s depletion mode GaAs MESFET clock recovery and decision circuit is described,which applies to the optical fiber communication.The circuit consists of a clock recovery circuit,including a preprocessor,phase detector(PD),low pass filter(LPF) and voltage controlled oscillator(VCO) and a decision circuit,including a comparator and a latch.The SPICE simulation result confirms the high frequency 2 5GHz of the clock recovery and the high speed 2 5Gb/s of the decision circuit.The 2 5Gb/s decision circuit has proved to be able to deal with the input signal and produce a digital output signal after it being sampled by a clock signal.
基金TheNationalHighTechnologyResearchandDevelopmentProgramofChina (863Program ) (No .2 0 0 2AA1Z160 0 )
文摘This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.
