Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Cus...Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.展开更多
The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extend...The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extended to the dummy sparse linear system. We apply the Gauss-Seidel method, which is one of the iterative methods for linear system, to the thermal model of floorplan of VLSI physical design. The experimental results of dummy sparse linear system are computed by using Gauss-Seidel method that have shown our theory analysis and extendibility. The iterative time of our incremental thermal model is 5 times faster than that of the inverting matrix method.展开更多
基金Project supported by the Hi-Tech Research and Development Pro-gram (863) of China (No. 2002AA1Z1140)the Fok Ying TongEducation Foundation (No. 94031), China
文摘Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel di- agonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network con- taining hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.
文摘The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extended to the dummy sparse linear system. We apply the Gauss-Seidel method, which is one of the iterative methods for linear system, to the thermal model of floorplan of VLSI physical design. The experimental results of dummy sparse linear system are computed by using Gauss-Seidel method that have shown our theory analysis and extendibility. The iterative time of our incremental thermal model is 5 times faster than that of the inverting matrix method.
