Y2000-62096-143 0010936体 CMOS 集成电路封锁保护用的提取简单布图规则的新试验法=New experimental methodology to extractcompact layout rules for latch prevention in bulk CMOSIC’s[会,英]/Ker,M.-D.& Lo,W.-Y.//Proceed-...Y2000-62096-143 0010936体 CMOS 集成电路封锁保护用的提取简单布图规则的新试验法=New experimental methodology to extractcompact layout rules for latch prevention in bulk CMOSIC’s[会,英]/Ker,M.-D.& Lo,W.-Y.//Proceed-ings of the IEEE 1999 Custom Integrated Circuits Con-ference.—143~146(UC)Y2000-62096-277 0010937高性能低功率用的定制电路技术(收录论文6篇)=Session 13:custom circuit techniques for high perfor-mance and low-power applications[会。展开更多
Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,m...Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.展开更多
A method for system-level simulation between microbolometer designing and Read-Out Integrated Circuit(ROIC) was studied. Three-dimensional(3D) structure modeling of the microbolometer was built. Thermal capacity, ther...A method for system-level simulation between microbolometer designing and Read-Out Integrated Circuit(ROIC) was studied. Three-dimensional(3D) structure modeling of the microbolometer was built. Thermal capacity, thermal conductivity and resistance of the model were obtained from thermoelectric coupling Finite Element Method(FEM) based on the model. An electrical equipment circuit of microbolometer which contains these three parameters was established. By using Verilog-AMS language, the electrical equipment circuit was described as a reduced-order macro-model. Then, the reduced-order macromodel was compiled in cadence to form IP unit of microbolometer, which could be used and identified in cadence. Systemlevel simulation between microbolometer and ROIC was accomplished. Key performances of the device, including input and output characteristics, were obtained in simulation and verified by experimental results.展开更多
文摘Y2000-62096-143 0010936体 CMOS 集成电路封锁保护用的提取简单布图规则的新试验法=New experimental methodology to extractcompact layout rules for latch prevention in bulk CMOSIC’s[会,英]/Ker,M.-D.& Lo,W.-Y.//Proceed-ings of the IEEE 1999 Custom Integrated Circuits Con-ference.—143~146(UC)Y2000-62096-277 0010937高性能低功率用的定制电路技术(收录论文6篇)=Session 13:custom circuit techniques for high perfor-mance and low-power applications[会。
文摘Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.
基金supported by the National Natural Science Foundation of China(Grant Nos.61235006 and 61421002)
文摘A method for system-level simulation between microbolometer designing and Read-Out Integrated Circuit(ROIC) was studied. Three-dimensional(3D) structure modeling of the microbolometer was built. Thermal capacity, thermal conductivity and resistance of the model were obtained from thermoelectric coupling Finite Element Method(FEM) based on the model. An electrical equipment circuit of microbolometer which contains these three parameters was established. By using Verilog-AMS language, the electrical equipment circuit was described as a reduced-order macro-model. Then, the reduced-order macromodel was compiled in cadence to form IP unit of microbolometer, which could be used and identified in cadence. Systemlevel simulation between microbolometer and ROIC was accomplished. Key performances of the device, including input and output characteristics, were obtained in simulation and verified by experimental results.