随着集成电路工艺进入微纳尺度,组合逻辑电路的软错误率不断增加,电路的可靠性受到严重威胁。传统的逻辑门加固结构通常会带来较大的面积开销。文章采用具有鲁棒容错性能的级联电压开关逻辑(cascade voltage switch logic,简称CVSL)门单...随着集成电路工艺进入微纳尺度,组合逻辑电路的软错误率不断增加,电路的可靠性受到严重威胁。传统的逻辑门加固结构通常会带来较大的面积开销。文章采用具有鲁棒容错性能的级联电压开关逻辑(cascade voltage switch logic,简称CVSL)门单元,提出"CVSL门对"结构对电路输出端进行选择性加固,以较小面积开销实现电路容错性能的大幅提升。Hspice仿真实验表明"CVSL门对"结构具有良好的容忍故障脉冲性能。ISCAS-89基准电路实验结果表明,被加固电路软错误防护率达90%以上,仅带来12.54%的面积开销,比CWSP单元加固法节省46.57%,比三模冗余结构加固法节省91.78%。展开更多
This paper presents a unique novel design of the phase-shifted cascade high voltage inverter. Thehigh voltage inverter utilizes fewer power switches and supplies a balance load. The usage of phase shifttransformer and...This paper presents a unique novel design of the phase-shifted cascade high voltage inverter. Thehigh voltage inverter utilizes fewer power switches and supplies a balance load. The usage of phase shifttransformer and phase shifting SPWM ensures that input and output harmonic wave content is low and outputvoltage change (du/dt) has a low rate, meeting all the requirements of the power authorities. The most out-standing feature is the energy saving with very fast cost recovery.展开更多
This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in ...This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.展开更多
文摘随着集成电路工艺进入微纳尺度,组合逻辑电路的软错误率不断增加,电路的可靠性受到严重威胁。传统的逻辑门加固结构通常会带来较大的面积开销。文章采用具有鲁棒容错性能的级联电压开关逻辑(cascade voltage switch logic,简称CVSL)门单元,提出"CVSL门对"结构对电路输出端进行选择性加固,以较小面积开销实现电路容错性能的大幅提升。Hspice仿真实验表明"CVSL门对"结构具有良好的容忍故障脉冲性能。ISCAS-89基准电路实验结果表明,被加固电路软错误防护率达90%以上,仅带来12.54%的面积开销,比CWSP单元加固法节省46.57%,比三模冗余结构加固法节省91.78%。
文摘This paper presents a unique novel design of the phase-shifted cascade high voltage inverter. Thehigh voltage inverter utilizes fewer power switches and supplies a balance load. The usage of phase shifttransformer and phase shifting SPWM ensures that input and output harmonic wave content is low and outputvoltage change (du/dt) has a low rate, meeting all the requirements of the power authorities. The most out-standing feature is the energy saving with very fast cost recovery.
文摘This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.
