A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor...A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.展开更多
A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins ...A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.展开更多
A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity re...A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.展开更多
The paper has presented the impact on the line protection performance with the introduction of MUs （merging units） in the process bus level. The paper begins with the introduction on modem digital substation structu...The paper has presented the impact on the line protection performance with the introduction of MUs （merging units） in the process bus level. The paper begins with the introduction on modem digital substation structure and process bus. Then, the paper describes the performances of different sensors such as CTs （current transformers）, CVTs （capacitive voltage transformers）, FOCS （fiber optical current transducers） and FOVS （fiber optical voltage transducers）. With the use of above transducers together with MUs, the performance of distance protection function and line differential protection function have been investigated and presented. Finally, conclusions based on the study are presented in the paper.展开更多
In this paper, hierarchical mesoporous Co3O4@ZnCo2O4 hybrid nanowire arrays（NWAs） on Ni foam were prepared through a two-step hydrothermal process associated with successive annealing treatment. The Co3O4@ZnCo2O4 hy...In this paper, hierarchical mesoporous Co3O4@ZnCo2O4 hybrid nanowire arrays（NWAs） on Ni foam were prepared through a two-step hydrothermal process associated with successive annealing treatment. The Co3O4@ZnCo2O4 hybrid NWAs exhibited excellent electrochemical performances with a high specific capacity of 1,240.5 C g^-1 at a current density of 2 mA cm^-2, with rate capability of 59.0%shifting from 2 to 30 mA cm^-2, and only a 9.1% loss of its capacity even after 3,000 cycles at a consistent current density of 10 mA cm^-2. An asymmetric supercapacitor（Co3O4@ZnCo2O4 NWAs｜｜activated carbon） was fabricated and exhibited a high specific capacity of 168 C g^-1 at a current density of 1 A g^-1. And a preferable energy density of 37.3 W h kg^-1 at a power density of 800 W kg^-1 was obtained. The excellent electrochemical performances indicate the promising potential application of the hierarchical mesoporous Co3O4@ZnCo2O4 hybrid NWAs in energy storage field.展开更多
文摘A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.
基金The Key Science and Technology Project of Zhejiang Province(No.2007C21021)
文摘A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.
文摘A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.
文摘The paper has presented the impact on the line protection performance with the introduction of MUs （merging units） in the process bus level. The paper begins with the introduction on modem digital substation structure and process bus. Then, the paper describes the performances of different sensors such as CTs （current transformers）, CVTs （capacitive voltage transformers）, FOCS （fiber optical current transducers） and FOVS （fiber optical voltage transducers）. With the use of above transducers together with MUs, the performance of distance protection function and line differential protection function have been investigated and presented. Finally, conclusions based on the study are presented in the paper.
基金supported by the National Natural Science Foundation of China (51571072)the Fundamental Research Funds for the Central Universities (AUGA5710012715)+1 种基金China Postdoctoral Science Foundation (2015M81436)Heilongjiang Postdoctoral Science Foundation (LBH-Z15065)
文摘In this paper, hierarchical mesoporous Co3O4@ZnCo2O4 hybrid nanowire arrays（NWAs） on Ni foam were prepared through a two-step hydrothermal process associated with successive annealing treatment. The Co3O4@ZnCo2O4 hybrid NWAs exhibited excellent electrochemical performances with a high specific capacity of 1,240.5 C g^-1 at a current density of 2 mA cm^-2, with rate capability of 59.0%shifting from 2 to 30 mA cm^-2, and only a 9.1% loss of its capacity even after 3,000 cycles at a consistent current density of 10 mA cm^-2. An asymmetric supercapacitor（Co3O4@ZnCo2O4 NWAs｜｜activated carbon） was fabricated and exhibited a high specific capacity of 168 C g^-1 at a current density of 1 A g^-1. And a preferable energy density of 37.3 W h kg^-1 at a power density of 800 W kg^-1 was obtained. The excellent electrochemical performances indicate the promising potential application of the hierarchical mesoporous Co3O4@ZnCo2O4 hybrid NWAs in energy storage field.
