A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins ...A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.展开更多
基金The Key Science and Technology Project of Zhejiang Province(No.2007C21021)
文摘A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.
