蓬勃发展的半导体光放大器市场

由于通信、专用仪器、军用、航天、私用数据网络等应用的需求牵引,半导体光放大器(SOA)市场兴旺,未来将保持蓬勃发展的势头,其发展前景引人注目。 半导体光放大器在结构上类似于半导体激光器,由有源区和无源区构成,有源区为增益区,使用InP这样的半导体材料制作,如图1所示。与半导体激光器的主要不同之处在于,SOA带抗反射涂层,目的在于防止光反射回来进入电路。

射频宽带放大器设计与实现

随着微电子技术的发展,小信号的处理在通信和信息处理领域运用越来越广泛,宽带运算放大器广泛应用于A/D转换器、D/A转换器,有源滤波仪、波形发生器、广播、电视、通信、雷达等的接收机等电路中,而对小信号的宽带增益可控和频带内增益起伏控制是当前的一个难题。以两级可控增益放大器AD603为核心,电流反馈型运放THS3091配合,实现了增益可调和频带内增益起伏控制的宽带直流放大器。系统主要由四个模块构成:前置放大电路、可控增益放大电路、后级功率放大电路、频带内增益起伏控制比较电路。

为有线电视网络系统改造提供的砷化镓方案(三)

本文的重点是集中在如何利用摩托罗拉半导体部出产的砷化嫁有线电视放大器模块的优点来设计用于有线电视网络的光工作站和延长线放大器。这些设计方案可以用于新建或改造的HFC光纤同轴混合网络上,显著提高光工作站和延长线放大器的性能。

自研20μm/400μm保偏光纤基于振荡器种子实现4 kW突破

高功率窄线宽光纤激光器在相干合成、光谱合成以及非线性频率转换等领域发挥了重要的作用,吸引了大量国内外研究人员的广泛关注。近年来,华中科技大学武汉光电国家研究中心光纤激光技术团队持续进行优秀的国产化高功率窄线宽线偏振光纤激光技术的研究工作,2022年,课题组采用基于振荡器的种子源加自研的保偏掺镱光纤先后实现单正向1.2 kW和单反向3.2 kW的线偏振窄线宽光纤激光输出。近期,课题组进一步优化保偏掺镱光纤的掺杂组分,并改良振荡器种子源设计来抑制窄线宽保偏放大过程中的TMI和受激布里渊散射(SBS)效应,最终实现了输出功率4.1 kW的窄线宽线偏振全光纤激光输出。

All-Optical Sampling Using Nonlinear Polarization Rotation in a Single Semiconductor Optical Amplifier

We propose a novel all-optical sampling method using nonlinear polarization rotation in a semiconductor optical amplifier. A rate-equation model capable of describing the all-optical sampling mechanism is presented in this paper. Based on this model, we investigate the optimized operating parameters of the proposed system by simulating the output intensity of the probe light as functions of the input polarization angle, the phase induced by the polarization controller, and the ori- entation of the polarization beam splitter. The simulated results show that we can obtain a good linear slope and a large linear dynamic range,which is suitable for all-optical sampling. The operating power of the pump light can be less than lmW. The presented all-optical sampling method can potentially operate at a sampling rate up to hundreds GS/s and needs low optical power.

Design and Fabrication of Power Si_(1-x)Ge_x/Si Heterojunction Bipolar Transistor for Wireless Power Amplifier Applications

A multi-finger structure power SiGe HBT device （with an emitter area of about 166μm^2） is fabricated with very simple 2μm double-mesa technology. The DC current gain β is 144.25. The B-C junction breakdown voltage reaches 9V with a collector doping concentration of 1 × 10^17cm^-3 and a collector thickness of 400nm. Though our data are influenced by large additional RF probe pads, the device exhibits a maximum oscillation frequency fmax of 10.1GHz and a cut-off frequency fτ of 1.8GHz at a DC bias point of IC=10mA and VCE = 2.5V.

Single-Stage Wide-Range CMOS VGA with Temperature Compensation and Linear-in-dB Gain Control

A novel wide-range CMOS variable gain amplifier （VGA） topology is presented. The proposed VGA is composed of a variable transconductor and a novel variable output resistor and can offer a high gain variation range of 80dB while using a single variable-gain stage. Temperature-compensation and decibel-linear gain characteristic are achieved by using a control circuit that provides a gain error lower than ±1.5dB over the full temperature and gain ranges. Realized in 0.25μm CMOS technology, a prototype of the proposed VGA provides a total gain range of 64.5dB with 55.6dB-linear range,a P-1dB varying from - 17.5 to 11.5dBm,and a 3dB-bandwith varying from 65 to 860MHz while dissipating 16.5mW from a 2.5V supply voltage.

A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications

A 2. 4GHz CMOS monolithic transceiver front-end for IEEE 802. llb wireless LAN applications is presented. The receiver and transmitter are both of superheterodyne structure for good system performance. The frontend consists of five blocks., low noise amplifier,down-converter, up-converter, pre-amplifier, and LO buffer. Their input/output impedance are all on-chip matched to 50 Ω except the down-converter which has open-drain outputs. The transceiver RF front-end has been implemented in a 0. 18μm CMOS process. When the LNA and the down-converter are directly connected, the measured noise figure is 5.2dB, the measured available power gain 12. 5dB, the input l dB compression point --18dBm,and the third-order input intercept point --7dBm. The receiver front-end draws 13.6mA currents from the 1.8V power supply. When the up-converter and pre-amplifier are directly connected, the measured noise figure is 12.4dB, the power gain is 23. 8dB, the output ldB compression point is 1.5dBm, and the third-order output intercept point is 16dBm. The transmitter consumes 27.6mA current from the 1.8V power supply.

Design of Low-Voltage Low Noise Amplifiers with High Linearity

A CMOS radio frequency low noise amplifier with high linearity and low operation voltage of less than 1.0V is presented.In this circuit,an auxiliary MOSFET in the triode region is used to boost the linearity.Simulation shows that this method can boost the input-referred 3rd-order intercept point with much less power dissipation than that of traditional power/linearity tradeoff solution which pays at least 1dB power for 1dB linearity improvement.It is also shown that the size of the common-gate PMOS transistor needs to be optimized to reduce its loaded input impedance so as not to degrade the linearity due to high voltage gain at its source terminal.The simulation is carried out with TSMC 0.18μm RF CMOS technology and SpectreRF.

A Wide-Band Low Noise Amplifier for Terrestrial and Cable Receptions

We present the design of a wide-band low-noise amplifier （LNA） implemented in 0.35μm SiGe BiCMOS technology for cable and terrestrial tuner applications. The LNA utilizes current injection to achieve high linearity. Without using inductors, the LNA achieves 0.1 ～ 1GHz wide bandwidth and 18. 8dB gain with less than 1.4dB of gain variation. The noise figure of the wideband LNA is 5dB, and its 1dB compression point is - 2dBm and IIP3 is 8dBm. The LNA dissipates 120mW of power with a 5V supply.

High performance differential CMOS LNA design for low-IF GPS receiver

A 1.575 GHz CMOS （complementary metal-oxidesemiconductor transistor） low noise amplifier（LNA） suitable for a low intermediate frequency（IF） global positioning system（GPS） receiver is presented. Considering parasitic effects resulting from bond pad and input electrostatic discharge （ESD） protection diodes, the optimization of the input matching and noise performance is analyzed, and a narrowband inductor model is applied to the circuit design and optimization. Based on the Volterra series, the nonlinearity of the LNA is analyzed and an equation describing input-referred third-order intercept points （IIP3） which indicate the nonlinearity effects is derived; accordingly, the trade-off between the power consumption and linearity is made. The LNA is designed and simulated with TSMC （Taiwan Semiconductor Manufacturing Company） 0. 18 μm radio frequency （RF）technology. Simulation results show that the LNA has a noise figure of only 1.1 dB, - 8. 3 dBm IIP3 with 3 mA current consumption from a 1.8 V voltage supply, and the input impedances match well.

An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

Measurement of linewidth enhancement factor of SOA using fiber Sagnac Ring

Semiconductor optical amplifiers (SOA) are optical amplifying devices and key parts in optical switches and optical buffers.They are largely used in communication system.Linewidth enhancement factor is an important parameter for SOA.A method is proposed to measure the linewidth enhancement factor with Sagnac interferometer.Cross phase modulation (XPM) and cross gain modulation (XGM) coexist in SOA.The quantitative relation of linewidth enhancement factor to XGM and the interference extinction ratio is given.The experimental results indicate that the value of linewidth enhancement factor changes from 5.13 to 6.24 when the electric current varies from 130 mA to 240 mA.

PCCP broken wire detection based on orthogonal electromagnetic principle

Aiming at the major failure mode of prestressed concrete cylinder pipes (PCCP),namely the fracture of prestressed steel wires,the broken wire detection technology based on orthogonal electromagnetic principle is studied. The detection system model is established and optimized by using COMSOL finite element simulation software. Furthermore,the theoretical analysis of the wire-breaking effect is carried out. The influence of factors on broken wire signal characteristics such as edge effect,circumferential relative position of the detector and broken wires,excitation frequency and relative permeability of steel wires is analyzed,which provides a theoretical guidance for the field detection. The influence of the steel cylinder structure on the simulation results is analyzed,which provides a reference for the improvement of calculation efficiency. The corresponding detection system is designed and implemented. Concretely,a high-voltage and high-power sinusoidal signal coil drive scheme based on sinusoidal pulse width modulation technology and an intelligent power module is innovatively proposed and the corresponding protection circuit is designed. The broken wire signal could be effectively extracted through a lock-in amplifier. The experimental results show that this system can effectively identify the broken wires with low cost.

130 nm CMOS Multi-Stage Synthetic Transmission Line Based Amplifier Beyond 100 GHz

A 130 nm CMOS complementary-conducting-strip transmission line(CCS-TL)based multi-stage amplifier beyond 100 GHz was presented in this paper. Different structural parameters were investigated to achieve higher quality factor for the matching circuits. Moreover, CCS-TL based Marchand balun was implemented to achieve higher output power. The measured small signal gain was higher than 5 d B from 101 GHz to 110 GHz. DC power consumption was 67.2 mW with V_D=1.2 V, and the chip size including contact PADs was 1.12 mm×0.81 mm.

Double Clad Er-doped Fiber Amplifier

Presented is a theoretical study of double-clad Er-doped fiber power amplifier(EDFA). Two kinds of double clad fibers(DCF) with rectangular and "flower" inner clad shapes are studied, and these fibers have different coupling constants and propagation losses. We calculate the effective pump power absorption ratio along the fiber with different coupling constants from the first cladding to the doped core and with different propagation losses for the power in the inner cladding. Then the gains of the double clad Er-doped fiber amplifiers versus fiber lengths are calculated using the EDFA model based on propagation and rate equations of a homogeneous, two-level medium.

Grey Self-similar Solitary Waves in Inhomogeneous Nonlinear Media

This paper analyzes spatial grey self-similar solitary waves propagation and collision in graded-index nonlinear waveguide amplifiers with self-focusing and self-defocusing Kerr nonlinearities. New exact self-similar solutions are found using a novel transformation and their main features are investigated by using direct computer simulations.

Noise and linearity optimization methods for a 1.9GHz low noise amplifier

Noise and linearity performances are critical characteristics for radio frequency integrated circuits (RFICs), especially for low noise amplifiers (LNAs). In this paper, a detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulating experiments. Theoretical analysis and simulation results showed that, for cascode structure LNAs, the first metallic oxide semiconductor field effect transistor (MOSFET) dominates the noise performance of the LNA, while the second MOSFET contributes more to the linearity. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade offs. The 1.9GHz Complementary Metal Oxide Semiconductor (CMOS) LNA simulation results are also given as an application of the developed theory.

Nonlinear Liquid Crystal Optical Signal Amplifiers

The principle, structure and system of nonlinear liquid crystal optical signal amplifiers are described. Experimental results are theoretically analysed for optical signal amplifers. It shows that this type of the optical signal amplifiers are comprised of liquid crystal light sensitive medium which can receive a modulated signal optic wave and a pump wave, and can be applied to optical transmission systems.

A PHEMT Based Wideband LNA for Wireless Applications

This work is about the development of a super low noise amplifier with minimum power consumption and high gain for several wireless applications.The amplifier operates at frequency bands of 0.9-2.4 GHz and can be used in many applications like Wireless local area network(WLAN),WiFi,Bluetooth,ZigBee and Global System for mobile communications(GSM).This new design can be employed for the IEEE 802.15.4 standard in industrial,scientific and medical(ISM) Band.The enhancement mode pseudomorphic high electron mobility transistor PHEMT is used here due to its high linearity,better performance and less noisy operation.The common source inductive degeneration method is employed here to enhance the gain of amplifier.The amplifier produces a gain of more than 17 dB and noise figure of about 0.5 dB.The lower values of S11 and S22 reflect the accuracy of impedance matching network placed at the input and output sides of amplifier.Agilent Advance Design System(ADS) is used for the design and simulation purpose.Further the layout of design is developed on the FR4 substrate.