一种交叉耦合低功耗传输门绝热逻辑电路

提出了一种新的能量恢复型电路—— Transmission Gate Adiabatic Logic(TGAL)。该电路由交叉耦合的 CMOS传输门完成逻辑运算与能量恢复 ,对负载的驱动为全绝热过程。TGAL电路输出端始终处于箝位状态 ,在整个输出期不存在悬空现象并具有良好的信号传输效果。分析了 TGAL反相器的能耗 ,并与静态 CMOS电路及部分文献中绝热电路进行了比较。使用 TGAL构成门电路与时序系统的实例被演示。应用 MOSIS的0 .2 5 μm CMOS工艺参数的模拟结果表明 ,与传统 CMOS和 2 N-2 N2 P绝热电路相比 ,TGAL电路在 1 0 0 MHz工作频率时分别节省 80 %与 60 %以上的功耗。

一种新型的绝热低功耗逻辑电路

文中作者提出了一种新型的自举式 Adiabatic逻辑电路—— Pass Transistor-Bootstrap Charge Recov-ery logic(PT-BCRL) ,该电路的操作分为两级 ,第一级负责逻辑值的运算 ,采用传统的 ECRL电路 ,第二级电路通过利用自举效应经 NMOS管对负载进行充放电 ,使得其充放电为一全绝热过程 ;另外 ,第一级电路通过一互补传输门与第二级电路相连 ,使得该电路的能量的传输和恢复效率都显著得到提高。由于电路分两级操作 ,它很好地解决了传统 Adiabatic电路的功耗和负载电容值直接相关的问题 ,这在用 0 .6μm

基于绝热电路三要素理论的绝热定时器设计

为了设计低功耗定时器,首先利用钟控传输门绝热逻辑电路设计绝热触发器,然后在分析C54X的定时器结构基础上,利用绝热电路三要素理论,结合钟控传输门绝热逻辑电路及其绝热触发器的特性,提出绝热定时器的设计新方案。最后,在采用TSMC 0.25μm CMOS工艺器件参数情况下,对依此理论设计的绝热定时器进行HSPCIE模拟,结果表明:该定时器逻辑功能正确,低功耗特性明显。

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

Design of adiabatic two's complement multiplier-accumulator based on CTGAL

We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two's complement multiplier-accumulator(MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor(CMOS) logic.