详细介绍了EM NMOST和AM PMOST组合的TF SOI CMOS非门下降时间的温度电学模型建立过程.分别进行了27,100,150,250,250,300 ℃的非门瞬态特性实验.实验结果表明,EM NMOST和AM PMOST组合的TF SOI CMOS非门的下降时间随温度升高稍有增加,...详细介绍了EM NMOST和AM PMOST组合的TF SOI CMOS非门下降时间的温度电学模型建立过程.分别进行了27,100,150,250,250,300 ℃的非门瞬态特性实验.实验结果表明,EM NMOST和AM PMOST组合的TF SOI CMOS非门的下降时间随温度升高稍有增加,非常适合于高温应用.如果对其进行优化设计,有利于改善其上升-下降时间温度特性的对称性,提高其最高工作频率.展开更多
Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) ...Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.展开更多
基金国家自然科学基金资助项目(批准号:69736020,60306003) Project supported by the National Natural Science Foundation of China(Nos. 69736020,60306003)
文摘详细介绍了EM NMOST和AM PMOST组合的TF SOI CMOS非门下降时间的温度电学模型建立过程.分别进行了27,100,150,250,250,300 ℃的非门瞬态特性实验.实验结果表明,EM NMOST和AM PMOST组合的TF SOI CMOS非门的下降时间随温度升高稍有增加,非常适合于高温应用.如果对其进行优化设计,有利于改善其上升-下降时间温度特性的对称性,提高其最高工作频率.
基金Project supported partially by the National Natural Science Foundation of China (Grant Nos. 60906038 and 61076082)
文摘Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.
