A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by...A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.展开更多
在鳍型场效应晶体管(SOI FinFET)相关静电防护技术研究基础上,提出了一种新型的体区接触固定型绝缘体上硅鳍型场效应晶体管泄放钳位装置(Fix-base SOI FinFET Clamp)。该新型结构的器件解决了基区接触浮空在静电防护设计时引起的一系列...在鳍型场效应晶体管(SOI FinFET)相关静电防护技术研究基础上,提出了一种新型的体区接触固定型绝缘体上硅鳍型场效应晶体管泄放钳位装置(Fix-base SOI FinFET Clamp)。该新型结构的器件解决了基区接触浮空在静电防护设计时引起的一系列问题,而且对正常的FinFET工艺具有良好的兼容性。通过计算机辅助工艺设计(TCAD)仿真论证了Fix-base SOI FinFET Clamp具有明显效果,详细阐述和讨论了SOI FinFET和Fix-base SOI FinFET Clamp工作状态下的电流和热分布。展开更多
SOI NLIGBT中热载流子效应分别通过直流电压的应力测试、TCAD仿真和电荷泵测试三种方法进行了研究。其中,不同直流电压应力条件下测得的衬底电流Isub和导通电阻Ron用来评估因热载流子效应引起的器件退化程度。为了进行理论分析,对器件...SOI NLIGBT中热载流子效应分别通过直流电压的应力测试、TCAD仿真和电荷泵测试三种方法进行了研究。其中,不同直流电压应力条件下测得的衬底电流Isub和导通电阻Ron用来评估因热载流子效应引起的器件退化程度。为了进行理论分析,对器件内部的电场强度和碰撞离化率也进行了仿真。测试得到的电荷泵电流直接验证了器件表面的损伤程度。最后讨论了SOI LIGBT在不同栅压条件下的退化机制。展开更多
A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channe...A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.展开更多
The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method dir...The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.展开更多
0.5μm-gate-length lateral double-diffused metal-oxide-semiconductor field-effect transistors （LDMOSFETs） with low barrier body contact （LBBC） and body tied to the source （BTS） were fabricated on silicon-on-insu...0.5μm-gate-length lateral double-diffused metal-oxide-semiconductor field-effect transistors （LDMOSFETs） with low barrier body contact （LBBC） and body tied to the source （BTS） were fabricated on silicon-on-insulator （SOI） substrates. The back-gate effects on front-channel subthreshold characteristics, on-resistance, and off-state breakdown characteristics of these devices are studied in detail. The LDMOSFETs with the LBBC structure show less back-gate effect than those with the BTS structure due to better control of the floating body effect and suppression of the parasitic backchannel leakage current. A model for the SOl LDMOSFETs has been given,including the front- and back-channel conductions as well as the bias-dependent series resistance.展开更多
文摘A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.
文摘在鳍型场效应晶体管(SOI FinFET)相关静电防护技术研究基础上,提出了一种新型的体区接触固定型绝缘体上硅鳍型场效应晶体管泄放钳位装置(Fix-base SOI FinFET Clamp)。该新型结构的器件解决了基区接触浮空在静电防护设计时引起的一系列问题,而且对正常的FinFET工艺具有良好的兼容性。通过计算机辅助工艺设计(TCAD)仿真论证了Fix-base SOI FinFET Clamp具有明显效果,详细阐述和讨论了SOI FinFET和Fix-base SOI FinFET Clamp工作状态下的电流和热分布。
基金The National Natural Science Foundation of China(No.61204083)the Natural Science Foundation of Jiangsu Province(No.BK2011059)the Program for New Century Excellent Talents in University(No.NCET-10-0331)
文摘A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.
基金special funds of major state basic research projects (G20000365)
文摘The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.
基金the National Natural Science Foundation of China(No.60576051)the State Key Development Program for Basic Research of China(No.2006CB3027-01)~~
文摘0.5μm-gate-length lateral double-diffused metal-oxide-semiconductor field-effect transistors （LDMOSFETs） with low barrier body contact （LBBC） and body tied to the source （BTS） were fabricated on silicon-on-insulator （SOI） substrates. The back-gate effects on front-channel subthreshold characteristics, on-resistance, and off-state breakdown characteristics of these devices are studied in detail. The LDMOSFETs with the LBBC structure show less back-gate effect than those with the BTS structure due to better control of the floating body effect and suppression of the parasitic backchannel leakage current. A model for the SOl LDMOSFETs has been given,including the front- and back-channel conductions as well as the bias-dependent series resistance.
