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活动目标的实时提取电路
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作者 姜凌涛 韩月秋 《大连理工大学学报》 EI CAS CSCD 北大核心 1997年第S2期137-137,共1页
活动目标的实时提取电路姜凌涛(中国科学院光电技术研究所成都610209)韩月秋(北京理工大学100081)电视监控系统中,自动提取出视场中的活动目标并进行报警是提高监控效率的重要途径。用软件实现处理,受处理速度的限制... 活动目标的实时提取电路姜凌涛(中国科学院光电技术研究所成都610209)韩月秋(北京理工大学100081)电视监控系统中,自动提取出视场中的活动目标并进行报警是提高监控效率的重要途径。用软件实现处理,受处理速度的限制,存在监控路数和采样周期的矛盾。本... 展开更多
关键词 实时提取 活动目标 目标提取 参考图像 大规模可编程逻辑器件 多帧平均 光电技术 中国科学院 缓冲器存储 二值图像
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IDT推出新型存储器缓冲器
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《电源世界》 2005年第1期13-13,共1页
全球领先的通信集成电路供应商IDT日前宣布推出新型存储器缓冲器,适用于多种全缓冲双插线存储器模块(FB-DIMM)的生产商。这个新产品完全兼容JEDEC的AMB标准,是下一代高带宽应用产品的必备技术,比如服务器和工作站,这些设备都要求更... 全球领先的通信集成电路供应商IDT日前宣布推出新型存储器缓冲器,适用于多种全缓冲双插线存储器模块(FB-DIMM)的生产商。这个新产品完全兼容JEDEC的AMB标准,是下一代高带宽应用产品的必备技术,比如服务器和工作站,这些设备都要求更高的性能和大型的存储容量。FB-DIMM信道架构的一个关键功能就是在信道中的存储控制器和模块之间实现高速度、 展开更多
关键词 存储缓冲器 AMB标准 JEDEC 存储控制器 IDT公司
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A Low-Power Super-Performance Four-Way Set-Associative CMOS Cache Memory 被引量:1
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作者 孙慧 李文宏 章倩苓 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2004年第4期366-371,共6页
A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel acce... A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved... 展开更多
关键词 CACHE set-associative sequential access parallel access current-mode sense amplifier COMPARATOR
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Approximate Models for CCN Data Transfer in General Topology
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作者 WANG Guoqing HUANG Tao LIU Jiang CHEN Jianya LIU Yunjie 《China Communications》 SCIE CSCD 2014年第7期40-47,共8页
Recently,Content-Centric Networking(CCN) has been paid more and more attention.The modeling of CCN as an important research point is the foundation of the architecture.The past work of cache network modeling always as... Recently,Content-Centric Networking(CCN) has been paid more and more attention.The modeling of CCN as an important research point is the foundation of the architecture.The past work of cache network modeling always assumes the virtual round trip time(VRTT) is zero for simplicity.However,this assumption isn't practical and results in model error especially in CCN.CCN's router can aggregate the content requests during the VRTT to avoid content delivery repeatedly.Thus,to modeling CCN data transfer,as well as understanding how it should be managed,the VRTT shouldn't be ignored.In this paper,we model the data transfer in CCN,and propose a multi-cache with aggregation approximation(MCAA)algorithm to get the content miss rate and VRTT at each router.Simulation results show the validity of our MCAA algorithm. 展开更多
关键词 CCN MCAA miss rate VRTT
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DESIGN AND IMPLEMENTATION OF SINGLE-BUFFERED ROUTERS
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作者 Hu Ximing Qu Jing +1 位作者 Wang Binqiang Wu Jiangxing 《Journal of Electronics(China)》 2007年第4期470-476,共7页
A Single-Buffered (SB) router is a router where only one stage of shared buffering is sandwiched between two interconnects in comparison of a Combined Input and Output Queued (CIOQ) router where a central switch f... A Single-Buffered (SB) router is a router where only one stage of shared buffering is sandwiched between two interconnects in comparison of a Combined Input and Output Queued (CIOQ) router where a central switch fabric is sandwiched between two stages of buffering. The notion of SB routers was firstly proposed by the High-Performance Networking Group (HPNG) of Stanford University, along with two promising designs of SB routers: one of which was Parallel Shared Memory (PSM) router and the other was Distributed Shared Memory (DSM) router. Admittedly, the work of HPNG deserved full credit, but all results presented by them appeared to relay on a Centralized Memory Management Algorithm (CMMA) which was essentially impractical because of the high processing and communication complexity. This paper attempts to make a scalable high-speed SB router completely practical by introducing a fully distributed architecture for managing the shared memory of SB routers. The resulting SB router is called as a Virtual Output and Input Queued (VOIQ) router. Furthermore, the scheme of VOIQ routers can not only eliminate the need for the CMMA scheduler, thus allowing a fully distributed implementation with low processing and commu- nication complexity, but also provide QoS guarantees and efficiently support variable-length packets in this paper. In particular, the results of performance testing and the hardware implementation of our VOIQ-based router (NDSC~ SR1880-TTM series) are illustrated at the end of this paper. The proposal of this paper is the first distributed scheme of how to design and implement SB routers publicized till now. 展开更多
关键词 Single-Buffered (SB) router Distributed Shared Memory (DSM) Parallel Shared Memory (PSM) Virtual Output and Input Queued (VOIQ) NDSC SR1880-T^TM router
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Design and elementary realization of the Vision Earth System
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作者 Narenna WU 《Global Geology》 2007年第1期59-64,共6页
The Vision Earth System is a interactive system by employing B/S model.The system has the function of query display and mutually displays relevant geologic information,integrating image information of one outcrop and ... The Vision Earth System is a interactive system by employing B/S model.The system has the function of query display and mutually displays relevant geologic information,integrating image information of one outcrop and realizing 3D geologic visualization.In this system,the basis is effective store,transmitting,display and quick query of enormous images and their properties data.From Java technology,this essay researches the elementary realization of Vision Earth System by adopting store formality of enormous images database,quick display image of website and quick image storage method. 展开更多
关键词 JAVA database storage buffer area image display
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Windows加速用微电路与多媒体出入口
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作者 柴振荣 《管理观察》 1996年第1期28-28,共1页
关键词 WINDOWS 微电路 加速器 Pentium微处理器 个人计算机 技术手段 存储缓冲器 图形控制器 光栅操作 填充操作
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Architecture of Intra Prediction for High Efficiency Video Coding
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作者 Jong-sik PARK Seong-soo LEE 《Journal of Measurement Science and Instrumentation》 CAS 2011年第4期364-366,共3页
This paper explains intra prediction method for High Efficiency Video Coding(HEVC).Intra prediction removes correlation of adjacent samples in spatial domain.Intra predictor requires reference images which are stored ... This paper explains intra prediction method for High Efficiency Video Coding(HEVC).Intra prediction removes correlation of adjacent samples in spatial domain.Intra predictor requires reference images which are stored in external memory.Memory access is required frequently in process of intra prediction.The proposed architecture can reduce external memory access by optimized internal buffer. 展开更多
关键词 High Efficiency Video Coding HEVC intraprediction low power
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