The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BI...The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.展开更多
A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm ...A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.展开更多
文摘The design of an FPGA（ field programmable gate array） based programmable SONET （synchronous optical network） OC-192 10 Gbit/s PRBS （pseudo-random binary sequence） generator and a bit interleaved polarity 8 （BIP-8） error detector is presented. Implemented in a parallel feedback configuration, this tester features PRBS generation of sequences with bit lengths of 2^7 - 1,2^10- 1,2^15 - 1,2^23 - land 2^31 - 1 for up to 10 Gbit/s applications with a 10 Gbit/s optical transceiver, via the SFI-4 （OC-192 serdes-framer interface）. In the OC-192 frame alignment circuit, a dichotomy search algorithm logic which performs the functions of word alignment and STM-64/OC192 de-frame speeds up the frame sync logic and reduces circuit complexity greatly. The system can be used as a low cost tester to evaluate the performance of OC-192 devices and components, taking the replacement of precious commercial PRBS testers.
文摘A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.
