UP-450无线电台的频率参数分析及编频方法

本文通过对UP－450等无线电台频率参数分析及编频方法的分析与研究，提出了一种利用计算机与通用编程器ALL－03（其它编程器也可）对UP－450等无线电台置频的方法。实验证明该方法简单、可靠、实用。

用微机实现GX-3000无线通信机工作频率编频

Gx-3000通信机为日本“Standond”公司产品,适合在超短波通信网中作为基地台或车载台。由于应用了微处理机技术(具体电路由2个单板微处理机LM6416ESUBu-COM及LC6502CMAIN-u-COM组成),可在任意频道内自动扫描,可频道优先或监视频道。VHF或UHF频段,频道数可达64个频道。该机工作频率电路采用PLL电路,其分频比将确定工作频率。PLL电路中的分频比由微处理机LC6502C输出决定,而微处理机输出则由LC6502c和EPROM(2716)之间的信息交换决定。该机频率预置由厂家用专用写入编频机来实现。经我们对该机进一步分析、研究、试验,认为可用一般微机或单板机对其实现编频。

实现GX-3000无线通信机编频的简便方法

《电子技术应用》1989年第6期上登载了《用微机实现GX-3000无线通信机工作频率编频》一文,其中对“GX-3000”通信机编频分析和微机实现编频的方法是正确的,并且有一定的使用价值。但是,目前有许多使用GX-3000通信机的单位尚未购置微机,缺少计算机方面的人材,用微机编频有一定的困难;而用手工计算,则速度慢,容易出错。针对上述情况。

FM4016UL/FM2516UL系列特高频无线电台编频的方法

本文介绍了FM4016UL/FM2516UL系列特高频无线电台编频制式程序和编频方法,以及给EPROM2716写入数据时应注意的问题。

一种移动通信设备PLL频率合成器的工作原理及编频方法

本文主要分析了UP-450频率合成器的系统组成及工作原理，并对频率参数进行了详细的讨论，提出了用计算机编程的方法。

A Programmable 2.4GHz CMOS Multi-Modulus Frequency Divider

A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.

Early all-zero blocks detecting method for video coding based on novel threshold

In order to decrease both computational complexity and coding time, an improved algorithm for the early detection of all-zero blocks （AZBs） in H. 264/AVC is proposed. The previous AZBs detection algorithms are reviewed. Three types of transformed frequency-domain coefficients, which are quantized to zeros, are analyzed. Based on the three types of frequencydomain scaling factors, the corresponding spatial coefficients are derived. Then the Schwarz inequality is applied to the derivation of the three thresholds based on spatial coefficients. Another threshold is set on the basis of the probability distribution of zero coefficients in a block. As a result, an adaptive AZBs detection algorithm is proposed based on the minimum of the former three thresholds and the threshold of zero blocks distribution. The simulation results show that, compared with the existing AZBs detection algorithms, the proposed algorithm achieves a 5% higher detection ratio in AZBs and 4% to 10% computation saving with only 0. 1 dB video quality degradation.

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.

Key technologies of frequency-hopping frequency synthesizer for Bluetooth RF front-end

A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.

Low Jitter,Dual-Modulus Prescalers for RF Receivers

Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is proposed to decrease the complexity of the circuit. A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process. The programmable ＆ pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process. The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable ＆ pulse swallow divider.

A VIDEO SPECTRUM SPLITTING ENCODING SCHEME BASED ON HUMAN VISION AND ITS COMPUTER SIMULATION

In this paper, a 3-D video encoding scheme suitable for digital TV/HDTV (high definition television) is studied through computer simulation. The encoding scheme is designed to provide a good match to human vision. Basically, this involves transmission of low frequency luminance information at full frame rate for good motion rendition and transmission of high frequency luminance signal at reduced frame rate for good detail in static images.

0.18μm CMOS programmable frequency divider design for DVB-T

The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.

Downlink cooperative beamforming for MIMO cellular systems

In downlink cellular multiple users in multiple cells systems using beams, the should cooperate to generate beams to improve the spectrum efficiency. A mathematical model for the multi-cell multi-user downlink transmission is established, and the gradients of the variables including beamfonning filters, receiving filters and transmitting power are calculated. Then, a gradient-project-based cooperative beamforming scheme is proposed in which each user iteratively adjusts bearnforming variables in the direction of the gradients and projects onto feasible spaces. The information exchange protocol needed to support the scheme is also described. Simulation results show that the proposed scheme can achieve an average spectral efficiency of about 5 bit/（ s · Hz · cell）. The results show that cooperative beamforming can improve the spectrum efficiency of the cellular systems.

Perceptual video coding method based on JND and AR model

In order to achieve better perceptual coding quality while using fewer bits, a novel perceptual video coding method based on the just-noticeable-distortion （JND） model and the auto-regressive （AR） model is explored. First, a new texture segmentation method exploiting the JND profile is devised to detect and classify texture regions in video scenes. In this step, a spatial-temporal JND model is proposed and the JND energy of every micro-block unit is computed and compared with the threshold. Secondly, in order to effectively remove temporal redundancies while preserving high visual quality, an AR model is applied to synthesize the texture regions. All the parameters of the AR model are obtained by the least-squares method and each pixel in the texture region is generated as a linear combination of pixels taken from the closest forward and backward reference frames. Finally, the proposed method is compared with the H.264/AVC video coding system to demonstrate the performance. Various sequences with different types of texture regions are used in the experiment and the results show that the proposed method can reduce the bit-rate by 15% to 58% while maintaining good perceptual quality.

Frequency-domain auto-adapting full waveform inversion with blended source and frequency-group encoding

As a high quality seismic imaging method, full waveform inversion （FWI） can accurately reconstruct the physical parameter model for the subsurface medium. However, application of the FWI in seismic data processing is computationally expensive, especially for the three-dimension complex medium inversion. Introducing blended source technology into the frequency-domain FWI can greatly reduce the computational burden and improve the efficiency of the inversion. However, this method has two issues： first, crosstalk noise is caused by interference between the sources involved in the encoding, resulting in an inversion result with some artifacts; second, it is more sensitive to ambient noise compared to conventional FWI, therefore noisy data results in a poor inversion. This paper introduces a frequency-group encoding method to suppress crosstalk noise, and presents a frequency- domain auto-adapting FWI based on source-encoding technology. The conventional FWI method and source-encoding based FWI method are combined using an auto-adapting mechanism. This improvement can both guarantee the quality of the inversion result and maximize the inversion efficiency.

Polarization state measurement based on photoelastic modulation

Polarization coding is a specific encoding method by using the polarization state of optical signal carrying coded in- formation. It focuses on nonlinear effects, polarization mode dispersion and other issues in high-speed fiber-optic communi- cations. This paper presents a measurement method for polarization state based on elastic-optic modulator. This method not only retains the original advantages of elastic-optic modulator for polarization measurement, but also overcomes the defects of existing methods including high modulation frequency and invalid collection by using array detector. Matlab simulation and experimental verification scheme are given. The feasibility of this method is verified through theoretical analysis, and simulation and experimental results are carried out. The error analysis of the measurement results shows that the method can meet the measurement requirements and provide conditions for using the polarization encoding in high-speed communication.

Design of 0.18 μm CMOS programmable frequency divider based on standard cells

The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.

Source extension based on ε-entropy

It is known by entropy theory that image is a source correlated with a certain characteristic of probability. The entropy rate of the source and ε- entropy (rate-distortion function theory) are the information content to identify the characteristics of video images, and hence are essentially related with video image compression. They are fundamental theories of great significance to image compression, though impossible to be directly turned into a compression method. Based on the entropy theory and the image compression theory, by the application of the rate-distortion feature mathematical model and Lagrange multipliers to some theoretical problems in the H.264 standard, this paper presents a new the algorithm model of coding rate-distortion. This model is introduced into complete test on the capability of the test model of JM61e (JUT Test Model). The result shows that the speed of coding increases without significant reduction of the rate-distortion performance of the coder.

RATE CONTROL ALGORITHM FOR H.264 VIDEO ENCODER

This letter proposes a rate control algorithm for H.264 video encoder, which is based on block activity and buffer state. Experimental results indicate that it has an excellent performance by providing much accurate bit rate and better coding efficiency compared with H.264. The computational complexity of the algorithm is reduced by adopting a novel block activity description method using the Sum of Absolute Difference (SAD) of 16× 16 mode, and its robustness is enhanced by introducing a feedback circuit at frame layer.