为了解决传统电压缓冲器建立时间较长、功耗较大等问题,提出了一种基于差分翻转电压跟随器(Differential Flipped Voltage Follower,DFVF)的AB类缓冲放大器。电路主要由作为输入级的DFVF和基于反相器的输出级组成。与其他缓冲器相比,该...为了解决传统电压缓冲器建立时间较长、功耗较大等问题,提出了一种基于差分翻转电压跟随器(Differential Flipped Voltage Follower,DFVF)的AB类缓冲放大器。电路主要由作为输入级的DFVF和基于反相器的输出级组成。与其他缓冲器相比,该电路结构简单,晶体管数量少。由于使用了AB类的缓冲器,因此输出电流不受偏置电流的影响,并且静态电流小。采用SMIC 0.18μm工艺对电路进行仿真,仿真结果表明在1.8 V电源电压、全电压摆幅下,能在0.56μs的建立时间内驱动1 n F的电容负载,同时静态电流只有5μA,可用于液晶显示器的列驱动。展开更多
Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback sh...Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.展开更多
The lack of standard to electronic circuits modeling made possible the development of many tools and modeling languages for electronic circuits. In this way, several tools to be used on different descriptions stage of...The lack of standard to electronic circuits modeling made possible the development of many tools and modeling languages for electronic circuits. In this way, several tools to be used on different descriptions stage of the designs are necessary. This paper presents a tool called SF^2HDL （Stateflow to Hardware Description Language or State Transition Table） that translates a finite state machine on state transition diagram representation, described by Stateflow tool, into an input file standard for TABELA program or into a file behavioral VHDL （Very High Speed Integrated Circuits Hardware Description Language） directly. The TABELA program was used to optimization this finite state machine. After that, the TAB2VHDL program was used to generate the VHDL code on register transfer level, what permits comparisons with results obtained by synthesis. The finite state machine must be described by Mealy model and the user can describe the machine on high level abstraction using all Simulink supports. The tool was very efficient on computational cost and it made translation of several cases, for the two VHDL description models. Every state machine translated was simulated and implemented on device EP2C20F484C7 using Quartus II environment.展开更多
文摘为了解决传统电压缓冲器建立时间较长、功耗较大等问题,提出了一种基于差分翻转电压跟随器(Differential Flipped Voltage Follower,DFVF)的AB类缓冲放大器。电路主要由作为输入级的DFVF和基于反相器的输出级组成。与其他缓冲器相比,该电路结构简单,晶体管数量少。由于使用了AB类的缓冲器,因此输出电流不受偏置电流的影响,并且静态电流小。采用SMIC 0.18μm工艺对电路进行仿真,仿真结果表明在1.8 V电源电压、全电压摆幅下,能在0.56μs的建立时间内驱动1 n F的电容负载,同时静态电流只有5μA,可用于液晶显示器的列驱动。
基金Foundation items:Fundamental Research Funds for the Central Universities(No.JUSRP51510)Primary Research&Development Plan of Jiangsu Province(No.BE2019003-2)。
文摘Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.
文摘The lack of standard to electronic circuits modeling made possible the development of many tools and modeling languages for electronic circuits. In this way, several tools to be used on different descriptions stage of the designs are necessary. This paper presents a tool called SF^2HDL （Stateflow to Hardware Description Language or State Transition Table） that translates a finite state machine on state transition diagram representation, described by Stateflow tool, into an input file standard for TABELA program or into a file behavioral VHDL （Very High Speed Integrated Circuits Hardware Description Language） directly. The TABELA program was used to optimization this finite state machine. After that, the TAB2VHDL program was used to generate the VHDL code on register transfer level, what permits comparisons with results obtained by synthesis. The finite state machine must be described by Mealy model and the user can describe the machine on high level abstraction using all Simulink supports. The tool was very efficient on computational cost and it made translation of several cases, for the two VHDL description models. Every state machine translated was simulated and implemented on device EP2C20F484C7 using Quartus II environment.
