This work demonstrates that the ΣΔ modulator with a low oversampling ratio is a viable option for the high-resolution digitization in a low-voltage environment.Low power dissipation is achieved by designing a low-OS...This work demonstrates that the ΣΔ modulator with a low oversampling ratio is a viable option for the high-resolution digitization in a low-voltage environment.Low power dissipation is achieved by designing a low-OSR modulator based on differential cascade architecture,while large signal swing maintained to achieve a high dynamic range in the low-voltage environment.Operating from a voltage supply of 1.8V,the sixth-order cascade modulator at a sampling frequency of 4-MHz with an OSR of 24 achieves a dynamic range of 81dB for a 80-kHz test signal,while dissipating only 5mW.展开更多
The formula for calculating the threshold of average transmitting power of cylindrical TE11 mode window is revised by accurate deduction and a practical method for calculating the temperature increment of the dielectr...The formula for calculating the threshold of average transmitting power of cylindrical TE11 mode window is revised by accurate deduction and a practical method for calculating the temperature increment of the dielectric disk in cylindrical box type window is given. Meanwhile,a typical cylindrical box type window is calculated and used as an example to discuss the power capacity, the special harmfulness and elimination of ghost mode resonance when the window is used to transmit high power Continuous Wave(CW).展开更多
Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementat...Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.展开更多
Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also propose...Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.展开更多
Cloud computing is becoming a key factor in the market day by day. Therefore, many companies are investing or going to invest in this sector for development of large data centers. These data centers not only consume m...Cloud computing is becoming a key factor in the market day by day. Therefore, many companies are investing or going to invest in this sector for development of large data centers. These data centers not only consume more energy but also produce greenhouse gases. Because of large amount of power consumption, data center providers go for different types of power generator to increase the profit margin which indirectly affects the environment. Several studies are carried out to reduce the power consumption of a data center. One of the techniques to reduce power consumption is virtualization. After several studies, it is stated that hardware plays a very important role. As the load increases, the power consumption of the CPU is also increased. Therefore, by extending the study of virtualization to reduce the power consumption, a hardware-based algorithm for virtual machine provisioning in a private cloud can significantly improve the performance by considering hardware as one of the important factors.展开更多
An upsurge of interest in relay-augmented infrastructure-based networks has appeared in recent years.Radio resource management in such relay systems has great influence on the system performance.How to utilize the lim...An upsurge of interest in relay-augmented infrastructure-based networks has appeared in recent years.Radio resource management in such relay systems has great influence on the system performance.How to utilize the limited frequency resources efficiently in the system is a hot research topic.In this paper,performance of frequency reuse schemes has been studied in fixed relay systems.A novel scheme is achieved by modifying an existing one.Theoretical model is proposed for the performance analysis of two schemes.Both the theoretical analysis and simulation results show that the modified scheme outperforms the existing one not only in power consumption of mobile stations but also in cell carrier-to-interference ratio coverage.展开更多
In distribution systems,network reconfiguration and capacitor placement are commonly used to diminish power losses and keep voltage profiles within acceptable limits.Moreover,the problem of DG allocation and sizing is...In distribution systems,network reconfiguration and capacitor placement are commonly used to diminish power losses and keep voltage profiles within acceptable limits.Moreover,the problem of DG allocation and sizing is great important.In this work,a combination of a fuzzy multi-objective approach and bacterial foraging optimization(BFO) as a meta-heuristic algorithm is used to solve the simultaneous reconfiguration and optimal sizing of DGs and shunt capacitors in a distribution system.Each objective is transferred into fuzzy domain using its membership function.Then,the overall fuzzy satisfaction function is formed and considered a fitness function inasmuch as the value of this function has to be maximized to gain the optimal solution.The numerical results show that the presented algorithm improves the performance much more than other meta-heuristic algorithms.Simulation results found that simultaneous reconfiguration with DG and shunt capacitors allocation(case 5) has 77.41%,42.15%,and 56.14%improvements in power loss reduction,load balancing,and voltage profile indices,respectively in 33-bus test system.This result found 87.27%,35.82%,and 54.34%improvements of mentioned indices respectively for 69-bus system.展开更多
文摘This work demonstrates that the ΣΔ modulator with a low oversampling ratio is a viable option for the high-resolution digitization in a low-voltage environment.Low power dissipation is achieved by designing a low-OSR modulator based on differential cascade architecture,while large signal swing maintained to achieve a high dynamic range in the low-voltage environment.Operating from a voltage supply of 1.8V,the sixth-order cascade modulator at a sampling frequency of 4-MHz with an OSR of 24 achieves a dynamic range of 81dB for a 80-kHz test signal,while dissipating only 5mW.
文摘The formula for calculating the threshold of average transmitting power of cylindrical TE11 mode window is revised by accurate deduction and a practical method for calculating the temperature increment of the dielectric disk in cylindrical box type window is given. Meanwhile,a typical cylindrical box type window is calculated and used as an example to discuss the power capacity, the special harmfulness and elimination of ghost mode resonance when the window is used to transmit high power Continuous Wave(CW).
文摘Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.
文摘Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.
基金supported by the National Research Foundation (NRF) of Korea through contract N-14-NMIR06
文摘Cloud computing is becoming a key factor in the market day by day. Therefore, many companies are investing or going to invest in this sector for development of large data centers. These data centers not only consume more energy but also produce greenhouse gases. Because of large amount of power consumption, data center providers go for different types of power generator to increase the profit margin which indirectly affects the environment. Several studies are carried out to reduce the power consumption of a data center. One of the techniques to reduce power consumption is virtualization. After several studies, it is stated that hardware plays a very important role. As the load increases, the power consumption of the CPU is also increased. Therefore, by extending the study of virtualization to reduce the power consumption, a hardware-based algorithm for virtual machine provisioning in a private cloud can significantly improve the performance by considering hardware as one of the important factors.
基金National Science Fund for Creative Research Groups(No.60521002)Chinese NationalKey Technology R&D Program(No.2005BA908B02)Science Foundation ofShanghai Municipal Commission of Scienceand Technology,Chinese(No.05dz05802)
文摘An upsurge of interest in relay-augmented infrastructure-based networks has appeared in recent years.Radio resource management in such relay systems has great influence on the system performance.How to utilize the limited frequency resources efficiently in the system is a hot research topic.In this paper,performance of frequency reuse schemes has been studied in fixed relay systems.A novel scheme is achieved by modifying an existing one.Theoretical model is proposed for the performance analysis of two schemes.Both the theoretical analysis and simulation results show that the modified scheme outperforms the existing one not only in power consumption of mobile stations but also in cell carrier-to-interference ratio coverage.
文摘In distribution systems,network reconfiguration and capacitor placement are commonly used to diminish power losses and keep voltage profiles within acceptable limits.Moreover,the problem of DG allocation and sizing is great important.In this work,a combination of a fuzzy multi-objective approach and bacterial foraging optimization(BFO) as a meta-heuristic algorithm is used to solve the simultaneous reconfiguration and optimal sizing of DGs and shunt capacitors in a distribution system.Each objective is transferred into fuzzy domain using its membership function.Then,the overall fuzzy satisfaction function is formed and considered a fitness function inasmuch as the value of this function has to be maximized to gain the optimal solution.The numerical results show that the presented algorithm improves the performance much more than other meta-heuristic algorithms.Simulation results found that simultaneous reconfiguration with DG and shunt capacitors allocation(case 5) has 77.41%,42.15%,and 56.14%improvements in power loss reduction,load balancing,and voltage profile indices,respectively in 33-bus test system.This result found 87.27%,35.82%,and 54.34%improvements of mentioned indices respectively for 69-bus system.
