Three kinds of coplanar waveguides （CPWs） are designed and fabricated on different silicon substrates---common low-resistivity silicon substrate （LRS）, LRS with a 3μm-thick silicon oxide interlayer, and high-resi...Three kinds of coplanar waveguides （CPWs） are designed and fabricated on different silicon substrates---common low-resistivity silicon substrate （LRS）, LRS with a 3μm-thick silicon oxide interlayer, and high-resistivity silicon （HRS） substrate. The results show that the microwave loss of a CPW on LRS is too high to be used, but it can be greatly reduced by adding a thick interlayer of silicon oxide between the CPW transmission lines and the LRS.A CPW directly on HRS shows a loss lower than 2dB/cm in the range of 0-26GHz and the process is simple,so HRS is a more suitable CPW substrate.展开更多
Major consideration dimensions for the physical layer design of wireless sensor network （WSN） nodes is analyzed by comparing different wireless communication approaches, diverse mature standards, important radio fre...Major consideration dimensions for the physical layer design of wireless sensor network （WSN） nodes is analyzed by comparing different wireless communication approaches, diverse mature standards, important radio frequency （RF） parameters and various microcontroller unit （MCU） solutions. An implementation of the WSN node is presented with experimental results and a novel ＂one processor working at two frequencies＂ energy saving strategy. The lifetime estimation issue is analyzed with consideration to the periodical listen required by common WSN media access control （MAC） algorithms. It can be concluded that the startup time of the RF which determines the best sleep time ratio and the shortest backoff slot time of MAC, the RF frequency and modulation methods which determinate the RX and TX current, and the overall energy consumption of the dual frequency MCU SOC （ system on chip） are the most essential factors for the WSN node physical layer design.展开更多
An efficient way to design a down-converter assembly for the Ka-band millimeter system is presented, in which dielectric resonators （DR＇s） are adopted in the Schottky barrier diode image recovery mixer and the loca...An efficient way to design a down-converter assembly for the Ka-band millimeter system is presented, in which dielectric resonators （DR＇s） are adopted in the Schottky barrier diode image recovery mixer and the local oscillator （LO）. DR structures guarantee high frequency stability with an acceptable volume. The configurations of low noise amplifier, mixer and oscillator in the assembly are described and fabricated to estimate the chain performance. According to the verification results, the assembly exhibits the noise figure of less than 5 dB over 1 GHz frequency range, and the single-sideband phase noise （200 kHz offset from carrier frequency） of - 70 dBc/Hz. Utilizing the DR structure, the frequency stability of the local oscillator is less than 60 × 10^-6/℃.展开更多
A low-power,high-frequency CMOS peak detector is proposed. This detector can detect RF signal and base-band signal peaks. The circuit is designed using SMIC 0.35μm standard CMOS technology. Both theoretical calculati...A low-power,high-frequency CMOS peak detector is proposed. This detector can detect RF signal and base-band signal peaks. The circuit is designed using SMIC 0.35μm standard CMOS technology. Both theoretical calculations and post simulations show that the detection error is no more than 2% for various temperatures and processes when the input amplitude is larger than 400mV. The detection bandwidth is up to 10GHz, and its static current dissipation is less than 20μA.展开更多
The objective of the study was to explore the effect of acute low temperature stress on VO2 and Vf of Silurus meridionalis and Pelteobag vachelli after 10 minutes cold water bath with different temperature.The investi...The objective of the study was to explore the effect of acute low temperature stress on VO2 and Vf of Silurus meridionalis and Pelteobag vachelli after 10 minutes cold water bath with different temperature.The investigation was operated under the temperature of 24 ℃.It was found that the VO2 and Vf of Silurus meridionalis after 6 and 0 ℃ stress showed a decrease-increase-decrease trend while other groups showed a rapid increase then slowly recovery trend.The VO2 and Vf of Pelteobag vachelli after 0 ℃stress showed a decrease-increase-decrease trend while other groups showed an increase then slowly recovery process.It was suggested that Pelteobag vachelli was more adaptive to acute cold stress,but it cost more energy adapting to cold stress compared to Silurus meridionalis.展开更多
The insertion loss （IL） of a T-type attenuator is theoretically analyzed. A T-type RF （ radio frequency） CMOS （ complementary metal-oxide-semiconductor ） attenuator is designed as an on-off keying（OOK） modulat...The insertion loss （IL） of a T-type attenuator is theoretically analyzed. A T-type RF （ radio frequency） CMOS （ complementary metal-oxide-semiconductor ） attenuator is designed as an on-off keying（OOK） modulator in a time-hopping ultra wide-band （TH-UWB）communication with a carrier frequency of 4 GHz. In the topology of the OOK modulator circuit, there are three parts, an oscillator with an oscillating frequency of 4 GHz, a T-type attenuator constructed by RF CMOS transistors, and an output impedance matching network with a L-type LC structure. The modulator is controlled by a time-hopping pulse position modulation（TH-PPM） signal. The envelope of the modulated signal varies with the amplitude of the controlling signal. Meanwhile, an output matching network is also designed to match a 50 Ω load. In 0. 18 μm RF CMOS technology, a modulator is designed and simulated. The implemented modulator chip has 65 mV of the output amplitude at a 50 fl load from a 1.8 V supply, and the return loss （ S11 ） at the output port is less than - 10 dB. The chip size is 0. 7 mm × 0. 8 mm, and the power consumption is 12. 3 mW.展开更多
An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are b...An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.展开更多
A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performanc...A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.展开更多
A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:...A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.展开更多
2D-to-3D video conversion is a feasible way to generate 3D programs for the current 3DTV industry. However, for large-scale 3D video production, current systems are no longer adequate in terms of the time and labor re...2D-to-3D video conversion is a feasible way to generate 3D programs for the current 3DTV industry. However, for large-scale 3D video production, current systems are no longer adequate in terms of the time and labor required for conversion. In this paper, we introduce a distributed 2D-to-3D video conversion system that includes a 2D-to-3D video conversion module, architecture of the parallel computation on the cloud, and 3D video coding in the system. The system enables cooperation among multiple users in the simultaneous completion of their conversion tasks so that the conversion efficiency is greatly promoted. In the experiments, we evaluate the system based on criteria related to both time consumption and video coding performance.展开更多
This paper presents a method to reduce the energy consumption of multi-core systems characterized by processor cores and buses with discrete frequency levels under timing constraints.The proposed method takes the tran...This paper presents a method to reduce the energy consumption of multi-core systems characterized by processor cores and buses with discrete frequency levels under timing constraints.The proposed method takes the transformations of the original task graphs,which include dependent tasks located in different iterations,as inputs.The proposed method utilizes mapping selection as well as joint processor and communication frequency scaling to implement energy reduction.We conduct experiments on several random task graphs.Experimental results show that the proposed method can achieve substantial energy reduction compared with previous work under the same hard timing constraints.展开更多
This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled g...This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.展开更多
文摘Three kinds of coplanar waveguides （CPWs） are designed and fabricated on different silicon substrates---common low-resistivity silicon substrate （LRS）, LRS with a 3μm-thick silicon oxide interlayer, and high-resistivity silicon （HRS） substrate. The results show that the microwave loss of a CPW on LRS is too high to be used, but it can be greatly reduced by adding a thick interlayer of silicon oxide between the CPW transmission lines and the LRS.A CPW directly on HRS shows a loss lower than 2dB/cm in the range of 0-26GHz and the process is simple,so HRS is a more suitable CPW substrate.
基金The National High Technology Research and Deve-lopment Program of China (863Program) (No.2003AA143040).
文摘Major consideration dimensions for the physical layer design of wireless sensor network （WSN） nodes is analyzed by comparing different wireless communication approaches, diverse mature standards, important radio frequency （RF） parameters and various microcontroller unit （MCU） solutions. An implementation of the WSN node is presented with experimental results and a novel ＂one processor working at two frequencies＂ energy saving strategy. The lifetime estimation issue is analyzed with consideration to the periodical listen required by common WSN media access control （MAC） algorithms. It can be concluded that the startup time of the RF which determines the best sleep time ratio and the shortest backoff slot time of MAC, the RF frequency and modulation methods which determinate the RX and TX current, and the overall energy consumption of the dual frequency MCU SOC （ system on chip） are the most essential factors for the WSN node physical layer design.
文摘An efficient way to design a down-converter assembly for the Ka-band millimeter system is presented, in which dielectric resonators （DR＇s） are adopted in the Schottky barrier diode image recovery mixer and the local oscillator （LO）. DR structures guarantee high frequency stability with an acceptable volume. The configurations of low noise amplifier, mixer and oscillator in the assembly are described and fabricated to estimate the chain performance. According to the verification results, the assembly exhibits the noise figure of less than 5 dB over 1 GHz frequency range, and the single-sideband phase noise （200 kHz offset from carrier frequency） of - 70 dBc/Hz. Utilizing the DR structure, the frequency stability of the local oscillator is less than 60 × 10^-6/℃.
文摘A low-power,high-frequency CMOS peak detector is proposed. This detector can detect RF signal and base-band signal peaks. The circuit is designed using SMIC 0.35μm standard CMOS technology. Both theoretical calculations and post simulations show that the detection error is no more than 2% for various temperatures and processes when the input amplitude is larger than 400mV. The detection bandwidth is up to 10GHz, and its static current dissipation is less than 20μA.
基金Supported by the National Natural Science Foundation of China(30371121)the Natural Science Foundation of Chongqing the Educa-tion Committee Foundation of Chongqing~~
文摘The objective of the study was to explore the effect of acute low temperature stress on VO2 and Vf of Silurus meridionalis and Pelteobag vachelli after 10 minutes cold water bath with different temperature.The investigation was operated under the temperature of 24 ℃.It was found that the VO2 and Vf of Silurus meridionalis after 6 and 0 ℃ stress showed a decrease-increase-decrease trend while other groups showed a rapid increase then slowly recovery trend.The VO2 and Vf of Pelteobag vachelli after 0 ℃stress showed a decrease-increase-decrease trend while other groups showed an increase then slowly recovery process.It was suggested that Pelteobag vachelli was more adaptive to acute cold stress,but it cost more energy adapting to cold stress compared to Silurus meridionalis.
文摘The insertion loss （IL） of a T-type attenuator is theoretically analyzed. A T-type RF （ radio frequency） CMOS （ complementary metal-oxide-semiconductor ） attenuator is designed as an on-off keying（OOK） modulator in a time-hopping ultra wide-band （TH-UWB）communication with a carrier frequency of 4 GHz. In the topology of the OOK modulator circuit, there are three parts, an oscillator with an oscillating frequency of 4 GHz, a T-type attenuator constructed by RF CMOS transistors, and an output impedance matching network with a L-type LC structure. The modulator is controlled by a time-hopping pulse position modulation（TH-PPM） signal. The envelope of the modulated signal varies with the amplitude of the controlling signal. Meanwhile, an output matching network is also designed to match a 50 Ω load. In 0. 18 μm RF CMOS technology, a modulator is designed and simulated. The implemented modulator chip has 65 mV of the output amplitude at a 50 fl load from a 1.8 V supply, and the return loss （ S11 ） at the output port is less than - 10 dB. The chip size is 0. 7 mm × 0. 8 mm, and the power consumption is 12. 3 mW.
文摘An integrated low power CMOS VCO and its divide by 2 dividers for WLAN transceivers are presented.The VCO is based on on chip symmetrical spiral inductor and differential diode and the divide by 2 dividers are based on the ILFD technique.Due to differential LC tanks and ILFD techniques,power consumption is low.The circuit is implemented in a 0 18μm CMOS process.Measurements show the proposed circuit could produce 3 6/1 8GHz dual band LO signals with a wide tuning range and low phase noise.1 8GHz LO signals are quadrature.It consumes 5mA at V DD =1 5V.The size of die area is only 1 0mm×1 0mm.
文摘A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.
基金Project supported by the Second Stage of Brain Korea 21
文摘A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.
基金supported by the National Key Basic Research Program of China (973 Program) under Grant No. 2009CB320904the National Natural Science Foundation of China under Grants No. 61121002, No. 61231010, 91120004the Key Projects in the National Science and Technology Pillar Program under Grant No. 2011BAH08B03
文摘2D-to-3D video conversion is a feasible way to generate 3D programs for the current 3DTV industry. However, for large-scale 3D video production, current systems are no longer adequate in terms of the time and labor required for conversion. In this paper, we introduce a distributed 2D-to-3D video conversion system that includes a 2D-to-3D video conversion module, architecture of the parallel computation on the cloud, and 3D video coding in the system. The system enables cooperation among multiple users in the simultaneous completion of their conversion tasks so that the conversion efficiency is greatly promoted. In the experiments, we evaluate the system based on criteria related to both time consumption and video coding performance.
文摘This paper presents a method to reduce the energy consumption of multi-core systems characterized by processor cores and buses with discrete frequency levels under timing constraints.The proposed method takes the transformations of the original task graphs,which include dependent tasks located in different iterations,as inputs.The proposed method utilizes mapping selection as well as joint processor and communication frequency scaling to implement energy reduction.We conduct experiments on several random task graphs.Experimental results show that the proposed method can achieve substantial energy reduction compared with previous work under the same hard timing constraints.
文摘This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.
