A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel acce...A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...展开更多
The paper design mobile information collection system based on lnternet of Things, implemented access gateway by smart mobile devices through a variety of ways, such as Wi-Fi and access the underlying perceptual infor...The paper design mobile information collection system based on lnternet of Things, implemented access gateway by smart mobile devices through a variety of ways, such as Wi-Fi and access the underlying perceptual information based on ZigBee wireless sensor networks. On the one hand, For information sensitivity of the sensor network, we design the mobile terminal through the gateway access authentication protocol, and effective solute the authentication and infbnnation between mobile devices and gateways, gateway and sensor network nodes obtain permission problem; on the other hand, according to the practical application of mobile information collection characteristics, the paper proposed information collection strategy based on historical data movement path to solve the problem for too long the device connection is established when the mobile smart devices collecting information along fixed lines, increasing the actual data transmission time and improve the efficiency of information transmission.展开更多
文摘A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...
文摘The paper design mobile information collection system based on lnternet of Things, implemented access gateway by smart mobile devices through a variety of ways, such as Wi-Fi and access the underlying perceptual information based on ZigBee wireless sensor networks. On the one hand, For information sensitivity of the sensor network, we design the mobile terminal through the gateway access authentication protocol, and effective solute the authentication and infbnnation between mobile devices and gateways, gateway and sensor network nodes obtain permission problem; on the other hand, according to the practical application of mobile information collection characteristics, the paper proposed information collection strategy based on historical data movement path to solve the problem for too long the device connection is established when the mobile smart devices collecting information along fixed lines, increasing the actual data transmission time and improve the efficiency of information transmission.
