This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure t...This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure to reduce the intersymbolinterference （ISI） of the communication chan nel. By employing inductive peaking technique for the highfrequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decisionfeedback equalizer optimizes the size of the CMLbased circuit such as D flipflops （DFF） and multiplex （MUX）, shortening the feedback path delay and speeding up the operation considerably. Designed in the 0. 181μm CMOS technology, the equalizer delivers 10Gb/s data over 18in FR4 trace with 28dB loss while drawing 27mW from a 1.8V supply. The overall chip area including pads is 0. 6 -0.7mm2.展开更多
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA10305)
文摘This paper presents a lOGb/s highspeed equalizer as the frontend of a receiver for backplane communication. The equalizer combines an analog equalizer and a twotap decisionfeedback equal izer in a halfrate structure to reduce the intersymbolinterference （ISI） of the communication chan nel. By employing inductive peaking technique for the highfrequency boost circuit, the bandwidth and the boost of the analog equalizer are improved. The decisionfeedback equalizer optimizes the size of the CMLbased circuit such as D flipflops （DFF） and multiplex （MUX）, shortening the feedback path delay and speeding up the operation considerably. Designed in the 0. 181μm CMOS technology, the equalizer delivers 10Gb/s data over 18in FR4 trace with 28dB loss while drawing 27mW from a 1.8V supply. The overall chip area including pads is 0. 6 -0.7mm2.
