介绍了一种基于脉冲频率调制(Pulse Frequency Modulation,简称PFM)技术的数控高压脉冲电源。它利用PFM调制电路对输出电压进行调整和稳压,由单片机控制输出电压的脉宽,具有功耗低,体积小,重量轻,绝缘性能好等特点,而且输出高压在1.5～2...介绍了一种基于脉冲频率调制(Pulse Frequency Modulation,简称PFM)技术的数控高压脉冲电源。它利用PFM调制电路对输出电压进行调整和稳压,由单片机控制输出电压的脉宽,具有功耗低,体积小,重量轻,绝缘性能好等特点,而且输出高压在1.5～2.5kV连续可调。对具有高可靠性的过流保护电路进行了设计研究,在保证安全性的同时,满足了中子管性能检测系统中对离子源的供电需求。展开更多
A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage change...A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.展开更多
文摘介绍了一种基于脉冲频率调制(Pulse Frequency Modulation,简称PFM)技术的数控高压脉冲电源。它利用PFM调制电路对输出电压进行调整和稳压,由单片机控制输出电压的脉宽,具有功耗低,体积小,重量轻,绝缘性能好等特点,而且输出高压在1.5～2.5kV连续可调。对具有高可靠性的过流保护电路进行了设计研究,在保证安全性的同时,满足了中子管性能检测系统中对离子源的供电需求。
文摘A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.
