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A Fractional-N CMOS DPLL with Self-Calibration
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作者 刘素娟 杨维明 +2 位作者 陈建新 蔡黎明 徐东升 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第11期2085-2091,共7页
A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works... A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider. 展开更多
关键词 digital phase-locked loop phase-frequency detector SELF-CALIBRATION voltage controlled oscillator FRACTIONAL-N
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Capacitor self-calibration technique used in time-interleaved successive approximation ADC
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作者 殷勤 戚韬 +1 位作者 吴光林 吴建辉 《Journal of Southeast University(English Edition)》 EI CAS 2006年第2期164-168,共5页
A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter (SA-ADC) is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC b... A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter (SA-ADC) is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC by adding an additional clock period. This circuit is used in a 10 bit 32 Msample/s time-interleaved SA- ADC. The chip is implemented with Chart 0. 25 μm 2. 5 V process and totally occupies an area of 1.4 mm× 1.3 mm. After calibration, the simulated signal-to-noise ratio (SNR) is 59. 586 1 dB and the spurious-free dynamic range (SFDR) is 70. 246 dB at 32 MHz. The measured signal-to-noise and distortion ratio (SINAD) is 44. 82 dB and the SFDR is 63. 760 4 dB when the ADC samples a 5.8 MHz sinusoid wave. 展开更多
关键词 capacitor self-calibration analog-to-digital converter successive approximation time-interleaved
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A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications 被引量:1
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作者 章华江 胡康敏 洪志良 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第7期1298-1304,共7页
A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is... A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage. 展开更多
关键词 short range device phase locked loop adaptive frequency calibration frequency synthesizer SIGMA-DELTA
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Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters
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作者 王沛 龙善丽 吴建辉 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第9期1369-1374,共6页
Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter (SA-ADC) are described. The calibration circuit works in parallel with the SAAD... Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter (SA-ADC) are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave. 展开更多
关键词 analog-to-digital converter successive approximation self-calibration techniques
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A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications
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作者 姜亚伟 李智群 +1 位作者 舒海涌 侯凝冰 《Journal of Southeast University(English Edition)》 EI CAS 2010年第1期6-10,共5页
A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant ac... A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator(VCO)are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature(IQ)signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency(RF) complementary metal oxide semiconductor transistor (CMOS)technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs. 展开更多
关键词 phase-locked loop phase noise auto frequency calibration ZIGBEE voltage controlled oscillator
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Decadal co-variability of the summer surface air temperature and soil moisture in China under global warming 被引量:5
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作者 SU MingFeng WANG HuiJun 《Chinese Science Bulletin》 SCIE EI CAS 2007年第11期1559-1565,共7页
The self-calibrating Palmer Drought Severity Index (PDSI) is calculated using newly updated ground observations of monthly surface air temperature (SAT) and precipitation in China. The co-variabilities of PDSI and SAT... The self-calibrating Palmer Drought Severity Index (PDSI) is calculated using newly updated ground observations of monthly surface air temperature (SAT) and precipitation in China. The co-variabilities of PDSI and SAT are examined for summer for the period 1961-2004. The results show that there exist decadal climate co-variabilities and strong nonlinear interactions between SAT and soil moisture in many regions of China. Some of the co-variabilities can be linked to global warming. In summer,sig-nificant decadal co-variabilities from cool-wet to warm-dry conditions are found in the east region of Northwest China,North China,and Northeast China. An important finding is that in the west region of Northwest China and Southeast China,pronounced decadal co-variabilities take place from warm-dry to cool-wet conditions. Because significant warming was observed over most areas of the global land surface during the past 20-30 years,the shift to cool-wet conditions is a unique phenomenon which may deserve much scientific attention. The nonlinear interactions between SAT and soil moisture may partly account for the observed decadal co-variabilities. It is shown that anomalies of SAT will greatly affect the climatic co-variabilities,and changes of SAT may bring notable influence on the PDSI in China. These results provide observational evidence for increasing risks of decadal drought and wet-ness as anthropogenic global warming progresses. 展开更多
关键词 联合可变性 土壤湿度 表面空气温度 自校准器
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A long-term in situ calibration system for chemistry analysis of seawater
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作者 Chun-yang TAN Bo JIN +2 位作者 Kang DING William E. SEYFRIED Jr. Ying CHEN 《Journal of Zhejiang University-Science A(Applied Physics & Engineering)》 SCIE EI CAS CSCD 2010年第9期701-708,共8页
An in situ calibration system is a versatile exploration instrument for electrochemical sensors investigating the biochemical properties of the marine environment. The purpose of this paper is to describe the design o... An in situ calibration system is a versatile exploration instrument for electrochemical sensors investigating the biochemical properties of the marine environment. The purpose of this paper is to describe the design of an auto-calibrating system for electrochemical (pH) sensors, which permits two-point in situ calibration, suitable for long-term measurement in deep sea aqueous environments. Holding multiple sensors, the instrument is designed to perform long-term measurements and in situ calibrations at abyssal depth (up to 4000 m). The instrument is composed of a compact fluid control system which is pressure-equilibrated and designed for deep-sea operation. In situ calibration capability plays a key role in the quality and reproducibility of the data. This paper focuses on methods for extending the lifetime of the instrument, considering the fluidics design, mechanical design, and low-power consumption of the electronics controller. The instrument can last 46 d under normal operating conditions, fulfilling the need for long-term operation. Data concerning pH measured during the KNOX18RR cruise (Mid-Atlantic Ridge, July-August, 2008) illustrate the desirable properties of the instrument. Combined with different electrodes (pH, H2, H2S, etc.), it should be of great utility for the study of deep ocean environments, including water column and diffuse-flow hydrothermal fluids. 展开更多
关键词 PH LONG-TERM In situ calibration Flow control Low power
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